Dual-port semiconductor memory and first-in first-out (FIFO) memory having electrically floating body transistor
First Claim
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1. A multi-port semiconductor memory cell comprising:
- a plurality of gates;
a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell; and
a plurality of conductive regions of a second conductivity type,wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions.
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Abstract
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
246 Citations
22 Claims
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1. A multi-port semiconductor memory cell comprising:
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a plurality of gates; a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell; and a plurality of conductive regions of a second conductivity type, wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15)
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9. The multi-port semiconductor memory cell of 7, wherein the fin structure further includes the plurality of conductive regions.
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16. A multi-port semiconductor memory cell comprising:
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a plurality of ports; a floating body transistor, wherein the floating body transistor includes a floating body region configured to store a charge that is indicative of the state of said memory cell; and a plurality of access transistors, wherein each one of said plurality of access transistors corresponds to a respective one of the plurality of ports, wherein the respective ones of said ports differ from one another. - View Dependent Claims (17)
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18. A semiconductor memory cell comprising:
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a plurality of transistors, wherein each of the plurality of transistors comprising; a common body region configured to store a charge that is indicative of the state of said memory cell; and a plurality of gates, wherein said common body region is shared among the plurality of transistors; a layer beneath said common body region wherein said common body region is positioned between said plurality of gates and said layer; and a terminal connected to said layer and configured to at least one of inject a charge into and extract the charge out of the common body region to maintain said memory state of the semiconductor memory cell.
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19. A multi-port semiconductor memory cell comprising:
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a plurality of gates; a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell; and a plurality of conductive regions of a second conductivity type, wherein one of the plurality of conductive regions separates each of the plurality of gates from the other of the plurality of gates; and wherein the plurality of conductive regions and the common body region form a plurality of diodes.
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20. A multi-port semiconductor memory cell comprising:
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a plurality of gates; a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell; and a plurality of conductive regions of a second conductivity type, wherein one of the plurality of conductive regions separates each of the plurality of gates from the other of the plurality of gates; and wherein the multi-port semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common body region.
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21. A multi-port semiconductor memory cell comprising:
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a plurality of gates; a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell; and a plurality of conductive regions of a second conductivity type, wherein one of the plurality of conductive regions separates each of the plurality of gates from the other of the plurality of gates; and wherein the multi-port semiconductor memory cell is formed on a substrate, wherein the multi-port semiconductor memory cell further includes a buried layer region, and further wherein the buried layer region separates the common body region from the substrate, wherein the buried layer region includes a conductive buried layer of the second conductivity type, wherein the substrate has the first conductivity type; and
wherein the conductive buried layer, the common body region, and at least one of said conductive regions of a second conductivity type form a bipolar device.
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22. A multi-port semiconductor memory cell comprising:
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a plurality of gates; a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell; and a plurality of conductive regions of a second conductivity type, wherein one of the plurality of conductive regions separates each of the plurality of gates from the other of the plurality of gates; and wherein the multi-port semiconductor memory cell is formed on a substrate of the second conductivity type, wherein the substrate includes a substrate terminal configured to receive a substrate bias voltage, wherein the common body region is configured to retain a charge, and further wherein a maximum charge of the common body region increases with an increase in the substrate bias voltage.
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Specification