Buffer die in stacks of memory dies and methods

• US 8,582,373 B2
• Filed: 08/31/2010
• Issued: 11/12/2013
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hollis, Timothy
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Huang, Min
• Application Number:
  US12/872,638
• Publication Number:
  US 20120051152A1
• Time in Patent Office: 1,169 Days
• Field of Search: 365/63, 365/52, 365/189.05, 711/170
• US Class Current: 365/189.05
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1003 Interface circuits for daisy chain or ring bus memory arrangements

Abstract

Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.

Claims

1. A device, comprising:

a stack of memory dies directly connected to one another;

a command die coupled to communicate with the stack of memory dies; and

a first buffer die stacked within the stack of memory dies, and coupled between the command die and a downstream memory die in the stack of memory dies, wherein the first buffer die is configured to communicate with the command die, and repeat a signal between the command die and a downstream memory die in the stack of memory dies;

a second buffer die stacked between the first buffer die and another downstream memory die in the stack of memory dies;

wherein at least one of the first and second buffer dies is configured to communicate with a memory die above the respective buffer die in the stack of memory dies and is configured to communicate with a memory die below the respective buffer die in the stack of memory dies, and wherein the first and second buffer dies are configured to repeat memory signals.

2. The device of claim 1, wherein at least one of the first and second buffer dies is also configured to function as a memory die.

3. The device of claim 1, further comprising a number of communication paths coupling the dies in the memory device, wherein at least one of the number of communication paths is chosen from a group consisting of inductively coupled communication paths and capacitively coupled communication paths.

4. The device of claim 1, further comprising a number of communication paths coupling the dies in the memory device, wherein at least one of the number of communication paths comprises a through silicon via.

5. The device of claim 4, wherein the at least one through silicon via comprises a bypass through silicon via.

6. The device of claim 1, wherein at least one of the first and second buffer dies is configured to communicate with the command die using a through silicon via.

7. The device of claim 1, wherein at least one of the first and second buffer dies is configured to communicate with the command die using a bypass through silicon via.

8. The device of claim 1, further including additional dies to form a system-in-package device.

21. The device of claim 1, wherein the command die includes logic configured to operate the memory dies.

22. The device of claim 21, wherein the command die is also configured to function as a memory die.

23. The device of claim 1, wherein the command die is located at an upstream end of the memory device.

24. The device of claim 1, wherein the command die is configured to interface between the memory dies and a processor.

25. The device of claim 1, wherein the command die is stacked with the stack of memory dies.

26. The device of claim 1, wherein the stack of memory dies includes an upstream memory die located between the command die and at least one of the first and second buffer dies.

27. The device of claim 1, wherein at least one of the first and second buffer dies is configured to repeat the signal in a downstream direction.

28. The device of claim 1, further comprising a communication path between at least two of the dies in the memory device.

29. The device of claim 28, wherein the communication path includes circuitry to communicate within at least one of the at least two of the dies in the memory device.

30. The device of claim 28, wherein the communication path comprises a bi-directional communication path.

31. The device of claim 28, wherein the communication path comprises a unidirectional communication path.

32. The device of claim 1, wherein the communication path is a communication path between the command die and at least one of the first and second buffer dies, and wherein the communication path does not include connections configured to communicate with any memory die of the stack of memory dies between the command die and the respective buffer die.

33. The device of claim 1, wherein at least one of the first and second buffer dies includes a power regulation circuit.

34. The device of claim 1, wherein the downstream memory die comprises a plurality of downstream memory dies.

35. The device of claim 1, wherein the command die is configured to send a first level signal to the first buffer die, and wherein the first buffer die is configured to send a second level signal to the second buffer die.

36. The device of claim 35, further comprising a bypass through silicon via, wherein the first level signal is sent through the bypass through silicon via.

37. The device of claim 35, further comprising a bypass through silicon via, wherein the second level signal is sent through the bypass through silicon via.

38. The device of claim 35, wherein the second buffer die is configured to send a third level signal to a location within the other downstream memory die.

9. A memory device, comprising:

a stack of memory dies directly connected to one another;

a command die stacked with the stack of memory dies;

a first buffer die stacked between the command die and a downstream memory die in the stack of memory dies; and

a second buffer die stacked between the first buffer die and another downstream memory die in the stack of memory dies;

wherein the first and second buffer dies are configured to repeat memory signals.

10. The memory device of claim 9, wherein the first buffer die is configured to repeat memory signals serially between the command die and the second buffer die, and the second buffer die is configured to serially repeat signals between the first buffer die to the memory dies downstream of the second buffer die.

11. The memory device of claim 9, wherein the command die is configured to communicate in parallel with both the first buffer die and the second buffer die.

12. The memory device of claim 9, wherein at least one of the buffer dies is configured to communicate with the command die using a bypass through silicon via.

13. The memory device of claim 12, wherein the second buffer die is configured to communicate with the command die using a bypass through silicon via.

14. The memory device of claim 13, wherein the second buffer die is configured to communicate with the first buffer die using a bypass through silicon via.

15. A memory device, comprising:

a stack of memory dies directly connected to one another;

a command die stacked with the stack of memory dies;

a first buffer die stacked within the stack of memory dies, and coupled between the command die and a downstream memory die in the stack of memory dies;

a second buffer die stacked between the first buffer die and another downstream memory die in the stack of memory dies;

wherein at least one of the first and second buffer dies is configured to communicate with the command die, and repeat signals between the command die and a memory die in the stack of memory dies, wherein the respective buffer die is configured to communicate with a memory die above the respective buffer die in the stack of memory dies and is configured to communicate with a memory die below the respective buffer die in the stack of memory dies, and wherein the first and second buffer dies are configured to repeat memory signals; and

a power regulation circuit in at least one of the first and second buffer dies.

16. The memory device of claim 15, wherein the power regulation circuit comprises a voltage boosting circuit.

17. The memory device of claim 15, wherein the power regulation circuit comprises a noise reduction circuit.

18. A method comprising:

transmitting a signal between a command die in a stacked memory device and a memory die in the stacked memory device;

repeating the signal at least once using a buffer die, wherein the buffer die is at an intermediate location in a transmission path between the command die and the memory die; and

wherein the memory die comprises one of a plurality of memory dies, and further including prioritizing data to be stored in the stacked memory device, and storing lower priority data in a memory die of the plurality of memory dies that is farther from the command die than a memory die of the plurality of memory dies in which higher priority data is stored.

19. The method of claim 18, wherein repeating the signal at least once using a buffer die includes repeating the first signal to the memory die, wherein the memory die is physically downstream from the command die and physically downstream from the buffer die.

20. The method of claim 18, wherein repeating the signal at least once using a buffer die includes repeating the signal to the memory die, wherein the memory die is physically downstream from the command die and physically upstream from the buffer die.