Buffer die in stacks of memory dies and methods
First Claim
Patent Images
1. A device, comprising:
- a stack of memory dies directly connected to one another;
a command die coupled to communicate with the stack of memory dies; and
a first buffer die stacked within the stack of memory dies, and coupled between the command die and a downstream memory die in the stack of memory dies, wherein the first buffer die is configured to communicate with the command die, and repeat a signal between the command die and a downstream memory die in the stack of memory dies;
a second buffer die stacked between the first buffer die and another downstream memory die in the stack of memory dies;
wherein at least one of the first and second buffer dies is configured to communicate with a memory die above the respective buffer die in the stack of memory dies and is configured to communicate with a memory die below the respective buffer die in the stack of memory dies, and wherein the first and second buffer dies are configured to repeat memory signals.
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Abstract
Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.
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Citations
38 Claims
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1. A device, comprising:
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a stack of memory dies directly connected to one another; a command die coupled to communicate with the stack of memory dies; and a first buffer die stacked within the stack of memory dies, and coupled between the command die and a downstream memory die in the stack of memory dies, wherein the first buffer die is configured to communicate with the command die, and repeat a signal between the command die and a downstream memory die in the stack of memory dies; a second buffer die stacked between the first buffer die and another downstream memory die in the stack of memory dies; wherein at least one of the first and second buffer dies is configured to communicate with a memory die above the respective buffer die in the stack of memory dies and is configured to communicate with a memory die below the respective buffer die in the stack of memory dies, and wherein the first and second buffer dies are configured to repeat memory signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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9. A memory device, comprising:
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a stack of memory dies directly connected to one another; a command die stacked with the stack of memory dies; a first buffer die stacked between the command die and a downstream memory die in the stack of memory dies; and a second buffer die stacked between the first buffer die and another downstream memory die in the stack of memory dies; wherein the first and second buffer dies are configured to repeat memory signals. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A memory device, comprising:
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a stack of memory dies directly connected to one another; a command die stacked with the stack of memory dies; a first buffer die stacked within the stack of memory dies, and coupled between the command die and a downstream memory die in the stack of memory dies; a second buffer die stacked between the first buffer die and another downstream memory die in the stack of memory dies; wherein at least one of the first and second buffer dies is configured to communicate with the command die, and repeat signals between the command die and a memory die in the stack of memory dies, wherein the respective buffer die is configured to communicate with a memory die above the respective buffer die in the stack of memory dies and is configured to communicate with a memory die below the respective buffer die in the stack of memory dies, and wherein the first and second buffer dies are configured to repeat memory signals; and a power regulation circuit in at least one of the first and second buffer dies. - View Dependent Claims (16, 17)
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18. A method comprising:
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transmitting a signal between a command die in a stacked memory device and a memory die in the stacked memory device; repeating the signal at least once using a buffer die, wherein the buffer die is at an intermediate location in a transmission path between the command die and the memory die; and wherein the memory die comprises one of a plurality of memory dies, and further including prioritizing data to be stored in the stacked memory device, and storing lower priority data in a memory die of the plurality of memory dies that is farther from the command die than a memory die of the plurality of memory dies in which higher priority data is stored. - View Dependent Claims (19, 20)
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Specification