Reduced complexity timing estimation for locating the position of a mobile terminal

• US 8,582,698 B2
• Filed: 05/10/2010
• Issued: 11/12/2013
• Est. Priority Date: 05/10/2010
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Andgart, Niklas, Axmon, Joakim
• Primary Examiner(s): Vlahos, Sophia
• Application Number:
  US12/776,637
• Publication Number:
  US 20110274220A1
• Time in Patent Office: 1,282 Days
• Field of Search: 375/260, 375/267, 375/340, 375/342, 375/347, 455/404.2, 455/456.1, 342/357.2, 342/357.21, 342/357.25, 342/357.26, 342/357.46, 342/357.47, 701/207, 701/213
• US Class Current: 375/342
• CPC Class Codes: G01S 1/04 Details
• CPC Class Codes: G01S 1/20 using a comparison of transit time of synchronised signals transmitted from non-directional antennas or antenna systems spaced apart, i.e. path-difference systems
• CPC Class Codes: G01S 5/02216 Timing or synchronisation of the receivers
• CPC Class Codes: G01S 5/10 Position of receiver fixed by co-ordinating a plurality of position lines defined by path-difference measurements , e.g. omega or decca systemsG01S5/12 takes precedence ; beacons and receivers cooperating therewith G01S1/306, G01S1/308
• CPC Class Codes: H04L 25/022 of frequency response
• CPC Class Codes: H04L 27/2663 Coarse synchronisation, e.g. by correlation
• CPC Class Codes: H04L 27/2672 Frequency domain
• CPC Class Codes: H04L 27/2675 Pilot or known symbols
• CPC Class Codes: H04L 27/2695 with channel estimation, e.g. determination of delay spread, derivative or peak tracking channel estimation H04L25/0202

Abstract

A method and corresponding apparatus are provided to reduce the complexity of calculations needed to determine the time of arrival of position reference signals transmitted from multiple cells. A scheduler determines at a given instance what portions of a search grid or search window to search. A timing estimation circuit operating under the control of the scheduler computes timing estimates and reports the timing estimates back to the scheduler. The scheduler uses the timing estimates reported by the detection circuit to scheduler subsequent searches of the search grid or search window.

Claims

1. A method of estimating the arrival time of a received reference signal, said method comprising:

scheduling, by a scheduler, a first set of timing hypotheses spanning one or more OFDM symbols for one or more cells;

detecting, by a detector, one or more reference signals corresponding to the first set of timing hypotheses by, for each hypothesis;

converting one or more OFDM symbols from a time domain into a frequency domain;

computing channel estimates by correlating one or more frequency domain OFDM symbols with a known reference signal based on said timing hypothesis;

computing timing based on said channel estimates;

computing, by said detector, timing estimates based on said detected reference signals;

reporting, by said detector, said timing estimates for the detected reference signals to said scheduler; and

scheduling a second set of timing hypotheses based on the reported timing of the detected reference signals.

2. The method of claim 1 wherein computing timing based on said channel estimates comprises:

computing a channel impulse response based on said channel estimates;

detecting peaks in said channel impulse response.

3. The method of claim 1 wherein converting one or more OFDM symbols from a time domain into a frequency domain comprises computing a Fourier transform of the received OFDM symbols.

4. The method of claim 1 wherein correlating one or more frequency domain OFDM symbols with a known reference signal based on said timing hypothesis comprises:

extracting selected subcarriers from said frequency domain OFDM symbols based on said timing hypothesis; and

multiplying the extracted subcarriers by a conjugate of the reference signal to compute the channel estimate for the selected subcarriers.

5. The method of claim 1 further comprising accumulating channel estimates from two or more frequency domain OFDM symbols in a channel estimate vector for two or more subcarriers.

6. The method of claim 2 wherein computing a channel impulse response based on said channel estimates comprises computing an Inverse Fourier Transform of a channel estimate vector comprising channel estimates for two or more subcarriers.

7. The method of claim 6 wherein detecting peaks in said channel impulse response comprises computing power estimates for a plurality of impulse response samples and detecting peaks based on said power estimates.

8. The method of claim 7 wherein detecting peaks in said channel impulse response comprises iteratively computing power estimates and accumulating said power estimates in a sample buffer.

9. The method of claim 7 wherein detecting peaks in said channel impulse response further comprises interpolating said power estimates to find peaks between impulse response samples.

10. The method of claim 2 wherein computing a channel impulse response comprises:

computing a channel impulse response for two or more hypotheses; and

combining the channel impulse responses for two or more hypotheses to obtain a filtered channel impulse response.

11. The method of claim 1 wherein computing timing based on said channel estimates comprises computing phase slope of a channel impulse response;

and

determining timing based on said phase slope.

12. A timing estimation circuit for estimating the arrival time of a received reference signals, said timing estimation circuit comprising a detection circuit and a scheduler:

said detection circuit being configured to;

detect reference signals corresponding to a first set of timing hypotheses provided by a scheduler;

compute timing estimates based on said detected reference signals by, for each hypothesis;

converting one or more OFDM symbols from a time domain into a frequency domain;

computing channel estimates by correlating one or more frequency domain OFDM symbols with a known reference signal based on said timing hypothesis;

computing timing based on said channel estimates;

report said timing estimates for the detected reference signals to said scheduler; and

said scheduler being configured to;

schedule said first set of timing hypotheses so as to span one or more OFDM symbols for one or more cells to be processed by said detection circuit; and

schedule a second set of timing hypotheses to be processed by said detection circuit based on said reported timing estimates provided by said detection circuit.

13. The timing estimation circuit of claim 12 wherein said detection circuit is configured to compute timing estimates based on said channel estimates by:

computing a channel impulse response based on said channel estimates;

detecting peaks in said channel impulse response.

14. The timing estimation circuit of claim 12 wherein said detection circuit is configured to convert one or more OFDM symbols from a time domain into a frequency domain by computing a Fourier transform of the received OFDM symbols.

15. The timing estimation circuit of claim 12 wherein said detection circuit is configured to correlate one or more frequency domain OFDM symbols with a known reference signal based on said timing hypothesis by:

extracting selected subcarriers from said frequency domain OFDM symbols based on said timing hypothesis; and

multiplying the extracted subcarriers by a conjugate of the reference signal to compute the channel estimate for the selected subcarriers.

16. The timing estimation circuit of claim 12 wherein said detection circuit is further configured to accumulate channel estimates from two or more frequency domain OFDM symbols in a channel estimate vector comprising channel estimates for two or more subcarriers.

17. The timing estimation circuit of claim 13 wherein said detection circuit is configured to compute a channel impulse response based on said channel estimates by computing an Inverse Fourier Transform of a channel estimate vector comprising channel estimates for two or more subcarriers.

18. The timing estimation circuit of claim 17 wherein said detection circuit is configured to detect peaks in said channel impulse response by computing power estimates for a plurality of impulse response samples and detecting peaks based on said power estimates.

19. The timing estimation circuit of claim 18 wherein said detection circuit is configured to detect peaks in said channel impulse response by iteratively computing power estimates and accumulating said power estimates in a sample buffer.

20. The timing estimation circuit of claim 18 wherein said detection circuit is configured to detect peaks in said channel impulse response further by interpolating said power estimates to find peaks between impulse response samples.

21. The timing estimation circuit of claim 13 wherein said detection circuit is configured to compute a channel impulse response by:

computing a channel impulse response for two or more hypotheses; and

combining the channel impulse responses for two or more hypotheses to obtain a filtered channel impulse response.

22. The timing estimation circuit of claim 12 wherein said detection circuit is configured to compute timing based on said channel estimates comprises computing phase slope of a channel impulse response;

and determining timing based on said phase slope.