Switch circuit and method of switching radio frequency signals

• US 8,583,111 B2
• Filed: 12/28/2010
• Issued: 11/12/2013
• Est. Priority Date: 10/10/2001
• Status: Expired due to Term

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Cable, James S.
• Primary Examiner(s): TIEU, BINH KIEN
• Application Number:
  US12/980,161
• Publication Number:
  US 20110092179A1
• Time in Patent Office: 1,050 Days
• Field of Search: 455/26.1, 455/78, 455/333, 455/425, 455/550.1, 455/556.1, 455/560, 340/572.1, 340/571, 323/220, 323/226, 323/270, 323/274, 323/285, 237/280, 237/281, 237/241, 237/472, 379/412, 379/413
• US Class Current: 455/433
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence
• CPC Class Codes: H03K 2017/0803 against radiation hardening
• CPC Class Codes: H04B 1/40 Circuits

Abstract

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Claims

1. A circuit, comprising:

(a) a first port configured to receive a first RF signal;

(b) a second port configured to receive a second RF signal;

(c) an RF common port;

(d) a first switch transistor grouping having a first node coupled to the first port and a second node coupled to the RF common port, wherein the first switch transistor grouping has a control node configured to receive a switch control signal (SW);

(e) a second switch transistor grouping having a first node coupled to the second port and a second node coupled to the RF common port, wherein the second switch transistor grouping has a control node configured to receive an inverse (SW_) of the switch control signal (SW);

(f) a first shunt transistor grouping having a first node coupled to the second port and a second node coupled to ground, wherein the first shunt transistor grouping has a control node configured to receive the switch control signal (SW); and

(g) a second shunt transistor grouping having a first node coupled to the first port and a second node coupled to ground, wherein the second shunt transistor grouping has a control node configured to receive the inverse (SW_) of the switch control signal (SW).

2. The circuit of claim 1, wherein the circuit is fabricated in a silicon-on-insulator (SOI) technology.

3. The circuit of claim 1, wherein the circuit is fabricated on an Ultra-Thin-Silicon (“

UTSi”

) substrate.

4. The circuit of claim 1, wherein the transistor groupings comprise MOSFET transistors formed in a thin silicon layer on a fully insulating sapphire wafer, and wherein the fully insulating sapphire wafer enhances performance characteristics of the circuit by reducing substrate coupling effects.

5. The circuit of claim 1, wherein the transistor groupings comprise a plurality of MOSFET transistors arranged in a stacked configuration.

6. The circuit of claim 5, wherein switch insertion loss is reduced by reducing on-resistances of the MOSFET transistors.

7. The circuit of claim 5, wherein switch isolation characteristics of the circuit are improved by reducing parasitic capacitance between nodes of the MOSFET transistors.

8. The circuit of claim 5, wherein the stacked MOSFET transistors include gate nodes coupled to respective and associated gate resistors, and wherein the gate resistors are configured to be coupled to a switching voltage.

9. The circuit of claim 8, wherein the gate resistors coupled to the transistor gate nodes of the first switch and shunt transistor groupings are configured to be commonly controlled by the switch control signal SW.

10. The circuit of claim 8, wherein the gate resistors coupled to the transistor gate nodes of the second switch and shunt transistor groupings are configured to be commonly controlled by the inverse switch control signal SW_.

11. The circuit of claim 8, wherein the MOSFET transistors are configured to have associated gate capacitance, wherein RC time constants associated with each MOSFET transistor within the transistor groupings are functions of the values of the gate resistors and the associated gate capacitance, and wherein the RC time constant of each transistor far exceeds a period of the RF input signals thereby causing RF voltages to be shared equally across the MOSFET transistors.

12. The circuit of claim 5, wherein a breakdown voltage across the plurality of stacked MOSFET transistors of a selected transistor grouping is effectively increased to n times a breakdown voltage of an individual MOSFET transistor in the selected transistor grouping, wherein n comprises the total number of MOSFET transistors in the selected transistor grouping.

13. The circuit of claim 5, wherein the circuit has an associated 1 dB compression point, and wherein the 1 dB compression point is increased using the stacked MOSFET transistor configuration.

14. The circuit of claim 5, configured to receive the first and second RF input signals with associated input power levels, and wherein increased input power levels can be accommodated by the circuit by increasing the number of MOSFET transistors per transistor grouping.

15. The circuit of claim 5, configured to receive the first and second RF input signals with associated input power levels, and wherein increased input power levels may be accommodated by the circuit by varying the physical size of the transistors used in implementing the transistor groupings.

16. A switch circuit, comprising:

(a) the circuit as set forth in claim 1;

(b) a control logic block, coupled to the circuit of claim 1, wherein the control logic block is configured to output the switch control signal (SW) and the inverse switch control signal (SW_); and

(c) a negative voltage generator, coupled to the control logic block, wherein the negative voltage generator is configured to receive a clocking input signal and a positive power supply voltage from an external power supply, and wherein the negative voltage generator is configured to output a negative power supply voltage.

17. The circuit of claim 16, wherein the circuit is integrated in an integrated circuit (IC) with a plurality of digital and analog circuits.

18. The circuit of claim 16, further including:

(a) an oscillator, wherein the oscillator is configured to output clocking input signals;

(b) a charge pump, coupled to the oscillator, wherein the oscillator is configured to input the clocking input signals, and wherein the charge pump is configured to output a negative power supply voltage;

(c) a logic circuit block, coupled to the charge pump, wherein the logic circuit block is configured to output control signals for use in controlling the switch and shunt transistor groupings;

(d) a level-shifting circuit, coupled to the logic circuit block and the circuit, wherein the level-shifting circuit is configured to reduce gate-to-drain, gate-to-source, and drain-to-source voltages of MOSFET transistors used to implement the transistor groupings; and

(e) an RF buffer circuit, coupled to the circuit, wherein the RF buffer circuit is configured to isolate RF signal energy from the charge pump and the logic circuit blocks.

19. The circuit of claim 18, wherein the charge pump comprises:

(a) at least two P-channel MOSFET transistors;

(b) at least two N-channel MOSFET transistors, wherein each N-channel MOSFET transistor is coupled in series with a respective and associated P-channel MOSFET transistor thereby forming a respective leg of the charge pump;

(c) at least one coupling capacitor coupling each leg of the charge pump coupled to a successive leg; and

(d) an output capacitor, coupled to an output leg of the charge pump;

wherein the charge pump is configured to generate the negative power supply voltage by alternately charging and discharging the coupling and output capacitors using non-overlapping input clocking signals to drive the P-channel and N-channel MOSFET transistors.

20. The circuit of claim 19, wherein the non-overlapping input clocking signals comprise two non-overlapping clock control signals, and wherein a first non-overlapping clock control signal controls the P-channel transistors, and wherein a second non-overlapping clock control signal controls the N-channel transistors.

21. The circuit of claim 19, wherein the P-channel and N-channel transistors comprise single-threshold transistors.

22. The circuit of claim 19, wherein a pulse shift circuit is configured to generate the non-overlapping input clocking signals.

23. The circuit of claim 19, wherein the non-overlapping input clocking signals are derived from the oscillator clocking input signals.

24. The circuit of claim 19, wherein the oscillator comprises a relaxation oscillator.

25. The circuit of claim 19, wherein the non-overlapping input clocking signals vary in voltage amplitude from −

Vdd to +Vdd.

26. The circuit of claim 18, wherein the level-shifting circuit comprises a plurality of inverters coupled together in a feedback configuration.

27. The circuit of claim 26, wherein the inverters comprise differential inverters having a first differential input, a second differential input, a logic input and a logic output, and wherein the level-shifting circuit comprises:

(a) an input inverter group comprising two input differential inverters, wherein a first input differential inverter is configured to receive a logic input signal (input) and to output a first logic input signal (in), and wherein a second input differential inverter is configured to receive the first logic input signal (in) and to output an inverse (in_) of the first logic input signal;

(b) a first inverter group comprising three differential inverters, wherein the logic output of a first inverter of the first inverter group is coupled to the first logic input signal (in), the logic output of the first inverter is coupled to a first differential input of an output inverter of the first inverter group, the logic output of a second inverter of the first inverter group is coupled to a second differential input of the output inverter of the first inverter group, and wherein the output inverter of the first inverter group is configured to output a first output signal (out); and

(c) a second inverter group comprising three differential inverters, wherein the logic output of a first inverter of the second inverter group is coupled to the inverse (in_) of the first logic input signal, the logic output of the first inverter of the second inverter group is coupled to a first differential input of an output inverter of the second inverter group, the logic output of a second inverter of the second inverter group is coupled to a second differential input of the output inverter of the second inverter group, and wherein the output inverter of the second inverter group is configured to output a second output signal (out_);

wherein the circuit is configured to provide the first output signal (out) as feedback and input to the logic input of the second inverter of the second inverter group, and wherein the circuit is configured to provide the second output signal (out_) as feedback and input to the logic input of the second inverter of the first inverter group.

28. The circuit of claim 27, wherein the switch and shunt transistor groupings are configured to be controlled by the first and second output signals.

29. The circuit of claim 26, wherein the level-shifting circuit is configured to shift the DC level of the logic input signal (input) without affecting the frequency response of the input signal.

30. A circuit, comprising:

(a) a first port means configured to be coupled to a first RF signal;

(b) a second port means configured to be coupled to a second RF signal;

(c) an RF common port means;

(d) a first stacked transistor switching means having a first node coupled to the first port means and a second node coupled to the RF common port means, wherein the first stacked transistor switching means has a control node configured to be coupled to a switch control signal (SW);

(e) a second stacked transistor switching means having a first node configured to be coupled to the second port means and a second node coupled to the RF common port means, wherein the second stacked transistor switching means has a control node configured to be coupled to an inverse (SW_) of the switch control signal (SW);

(f) a first stacked transistor shunting means having a first node coupled to the second port means and a second node coupled to ground, wherein the first stacked transistor shunting means has a control node configured to be coupled to the switch control signal (SW); and

(g) a second stacked transistor shunting means having a first node coupled to the first port means and a second node coupled to ground, wherein the second stacked transistor shunting means has a control node configured to be coupled to the inverse (SW_) of the switch control signal (SW).

31. A circuit, comprising:

(a) a first port configured to be coupled to a first RF signal;

(b) a second port configured to be coupled a second RF signal;

(c) an RF common port;

(d) a first switch transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said first switch transistor grouping has a first node coupled to the first port and a second node coupled to the RF common port, and wherein the first switch transistor grouping has a control node configured to be coupled to a switch control signal (SW);

(e) a second switch transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said second transistor grouping has a first node coupled to the second port and a second node coupled to the RF common port, and wherein the second switch transistor grouping has a control node configured to be coupled to an inverse (SW_) of the switch control signal (SW);

(f) a first shunt transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said first shunt transistor grouping has a first node coupled to the second port and a second node coupled to ground, and wherein the first shunt transistor grouping has a control node configured to be coupled to the switch control signal (SW); and

(g) a second shunt transistor grouping comprising a plurality of FETs arranged in a stacked configuration, wherein each of said FETs has a gate that is insulated from its channel, wherein said second shunt transistor grouping has a first node coupled to the first port and a second node coupled to ground, wherein the second shunt transistor grouping has a control node configured to be coupled to the inverse (SW _) of the switch control signal (SW).

32. The circuit of claim 31, wherein the circuit is fabricated in a silicon-on-insulator (SOI) technology.

33. The circuit of claim 31, wherein the circuit is fabricated on an Ultra-Thin-Silicon (“

UTSi”

) substrate.

34. The circuit of claim 31, wherein the FETs comprise MOSFET transistors formed in a thin silicon layer on a fully insulating sapphire wafer.

35. The circuit of claim 31, configured to switch RF signals having an operating period 1/Fo, wherein the gate of each FET has a capacitance Cg to its channel, and the gate is configured to be coupled to a control voltage via a gate resistor Rg having a value such that Rg * Cg >

1/Fo.

36. The circuit of claim 31, wherein the gate of each FET is configured to be coupled to a control voltage via a gate resistor Rg having a value of at least about 30 kΩ

.

37. The circuit of claim 31, wherein the stacked MOSFETs of each grouping of transistors is configured to share the signal voltage substantially equally without a need for ballast resistors parallel to a conduction path of such stacked MOSFETs, and wherein all Rg of the MOSFETs of each particular grouping are configured to be commonly controlled by a corresponding switching voltage.

38. The circuit of claim 37, wherein the gate resistors coupled to the transistor gate nodes of the second switch and shunt transistor groupings are commonly coupled to the inverse switch control signal SW_.

39. The circuit of claim 31, wherein the FETs are MOSFETs having associated gate capacitance and an associated gate resistor configured to couple the gate to a drive signal, wherein RC time constants associated with each MOSFET within the transistor groupings are functions of the associated gate resistors and the associated gate capacitances, and wherein the RC time constant of each transistor far exceeds a period of the RF input signals thereby configured to cause RF voltages to be shared equally across the MOSFETs.

40. The circuit of claim 31, wherein a breakdown voltage across the plurality of stacked MOSFET transistors of a selected transistor grouping is n times a breakdown voltage of an individual MOSFET transistor in the selected transistor grouping, wherein n comprises the total number of MOSFET transistors in the selected transistor grouping.

41. The circuit of claim 31, configured to have RF signals swing about a zero reference voltage.

42. The circuit of claim 31, wherein the first and second RF input signals are characterized by associated input power levels, and wherein increased input power levels can be accommodated by the circuit by varying the physical size of the transistors used in implementing the transistor groupings.

43. A switch circuit, comprising:

(a) the circuit as set forth in claim 31;

(b) a control logic block, coupled to the RF switch circuit, wherein the control logic block is configured to output the switch control signal (SW) and the inverse switch control signal (SW _; and

(c) a negative voltage generator, coupled to the control logic block, wherein the negative voltage generator is configured to receive a positive power supply voltage from an external power supply, and wherein the negative voltage generator is configured to output a negative power supply voltage.

44. A circuit, comprising:

(a) a first port configured to be coupled to a first RF signal;

(b) a second port configured to be coupled to a second RF signal;

(c) an RF common port;

(d) a first switch transistor grouping comprising a plurality of FETs having channels series coupled in a stacked configuration, one end of the series-connected channels being a first node coupled to the first port, the opposite end of the series-connected channels being a second node coupled to the RF common port, the first switch transistor grouping having a control node configured to be coupled to a first switch control signal and coupled to a gate of each of the plurality of FETs of the grouping via a corresponding gate impedance;

(e) a second switch transistor grouping comprising a plurality of FETs having channels series coupled in a stacked configuration, one end of the series-connected channels being a first node coupled to the second port, the opposite end of the series-connected channels being a second node coupled to the RF common port, the second switch transistor grouping having a control node configured to be coupled to a second switch control signal and coupled to a gate of each of the plurality of FETs of the grouping via a corresponding gate impedance;

(f) a first shunt transistor grouping comprising one or more FETs arranged in a stacked configuration, one end of the series-connected channels being a first node coupled to the second port, the opposite end of the series-connected channels being a second node coupled to ground, the first shunt transistor grouping having a control node configured to be coupled to the first switch control signal and coupled to a gate of each of the one or more FETs of the grouping via a corresponding gate impedance; and

(g) a second shunt transistor grouping comprising one or more FETs arranged in a stacked configuration, one end of the series-connected channels being a first node coupled to the first port, the opposite end of the series-connected channels being a second node coupled to ground, the second shunt transistor grouping having a control node configured to be coupled to the second switch control signal and coupled to a gate of each of the one or more FETs of the grouping via a corresponding gate impedance.

45. The circuit of claim 44, wherein each RF signal is characterized by a corresponding frequency F, each FET has a corresponding gate capacitance Cg, and the gate impedance of each FET in a stacked grouping of a plurality of FETs is a primarily resistive Rg and forms an RgCg product with the corresponding Cg of the FET to which it is connected, and RgCg is long compared to a period 1/F of the corresponding signal switched by the stacked FET grouping.

46. The circuit of claim 44, wherein the switch circuit is fabricated in a silicon-on-insulator (SOI) technology.

47. The circuit of claim 44, wherein the transistor groupings comprise MOSFET transistors formed in a thin silicon layer on a fully insulating sapphire wafer, and wherein the fully insulating sapphire wafer enhances performance characteristics of the RF switch by reducing substrate coupling effects.

48. The circuit of claim 47, wherein the MOSFET transistors are characterized by associated gate capacitance, wherein RC time constants associated with each MOSFET transistor within the transistor groupings are functions of the gate resistors and the associated gate capacitance, and wherein the RC time constant of each transistor far exceeds a period of the RF input signals, thereby causing RF voltages to be shared equally across the MOSFET transistors.

49. The circuit of claim 45, wherein a breakdown voltage across the plurality of stacked MOSFET transistors of a selected transistor grouping is effectively increased to n times a breakdown voltage of an individual MOSFET transistor in the selected transistor grouping, wherein n comprises the total number of MOSFET transistors in the selected transistor grouping.

50. A circuit, comprising:

(a) circuit of claim 44;

(b) a control logic block, coupled to the circuit, wherein the control logic block is configured to output the switch control signal (SW) and the inverse switch control signal (SW_); and

(c) a negative voltage generator, coupled to the control logic block, wherein the negative voltage generator is configured to receive a clocking input signal and a positive power supply voltage from an external power supply, and wherein the negative voltage generator is configured to output a negative power supply voltage.

51. The circuit of claim 50, further including:

(a) an oscillator, wherein the oscillator is configured to output clocking input signals;

(b) a charge pump, coupled to the oscillator, wherein the oscillator is configured to input the clocking input signals, and wherein the charge pump is configured to output a negative power supply voltage;

(c) a logic circuit block, coupled to the charge pump, wherein the logic circuit block is configured to output control signals for use in controlling the switch and shunt transistor groupings;

(d) a level-shifting circuit, coupled to the logic circuit block and the circuit, wherein the level-shifting circuit is configured to reduce gate-to-drain, gate-to-source, and drain-to-source voltages of MOSFET transistors used to implement the transistor groupings; and

(e) an RF buffer circuit, coupled to the circuit, wherein the RF buffer circuit is configured to isolate RF signal energy from the charge pump and the logic circuit blocks.

52. A circuit, comprising:

a) a first RF port configured to receive or output a first RF signal (RF1);

b) a second RF port configured to receive or output a second RF signal (RF2);

c) an RF common port;

d) a first switch transistor grouping having a first node coupled to the first RF port and a second node coupled to the RF common port, wherein the first switch transistor grouping has a control node configured to be coupled to a first switch control signal;

e) a second switch transistor grouping having a first node coupled to the second RF port and a second node coupled to the RF common port, wherein the second switch transistor grouping has a control node configured to be coupled to a second switch control signal;

f) a first shunt transistor grouping having a first node coupled to the second RF port and a second node coupled to ground, wherein the first shunt transistor grouping has a control node configured to be coupled to the first switch control signal; and

g) a second shunt transistor grouping having a first node coupled to the first RF port and a second node coupled to ground, wherein the second shunt transistor grouping has a control node configured to be coupled to the second switch control signal.

53. The circuit of claim 52, wherein the circuit comprises a single-pole, multi-throw RF switch.

54. The circuit of claim 52, wherein the circuit comprises a multi-pole, single-throw RF switch.

55. The circuit of claim 52, wherein the circuit comprises a multi-pole, multi-throw RF switch.

56. A circuit, comprising:

a) a first RF port configured to output or receive a first RF signal;

b) a second RF port configured to output or receive a second RF signal;

c) a switch transistor grouping having a first node coupled to the first RF port and a second node coupled to the second RF port, wherein the switch transistor grouping has a control node configured to be coupled to a first switch control signal (SW); and

d) a shunt transistor grouping having a first node coupled to the first RF port and a second node coupled to ground, wherein the shunt transistor grouping has a control node configured to be coupled to a second switch control signal (SW_);

wherein the circuit is fabricated in a fully integrated device, wherein the fully integrated device includes a negative voltage generator coupled to the circuit wherein the negative voltage generator is configured to generate a negative power supply voltage, and wherein the negative voltage generator comprises a charge pump circuit.

57. The circuit of claim 56, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single MOSFET.

58. The circuit of claim 56, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration.

59. The circuit of claim 56, wherein the switch transistor grouping comprises a first number of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a second number of MOSFETs arranged in a stacked configuration, and wherein the first number and the second number differ from one another.

60. A circuit, comprising:

(a) a first RF port configured to input or output a first RF signal (RF

     1);

(b) a second RF port configured to input or receive and outputting a second RF signal (RF2);

(c) an RF common port;

(d) a first switch transistor grouping having a first node coupled to the first RF port and a second node coupled to the RF common port, wherein the first switch transistor grouping has a control node configured to be coupled to a first switch control signal;

(e) a second switch transistor grouping having a first node coupled to the second RF port and a second node coupled to the RF common port, wherein the second switch transistor grouping has a control node configured to be coupled to a second switch control signal;

(f) a first shunt transistor grouping having a first node coupled to the second RF port and a second node coupled to ground, wherein the first shunt transistor grouping has a control node configured to be coupled to the first switch control signal; and

(g) a second shunt transistor grouping having a first node coupled to the first RF port and a second node coupled to ground, wherein the second shunt transistor grouping has a control node configured to be coupled to the second switch control signal;

wherein the circuit is fabricated in a fully integrated device, wherein the fully integrated device includes a negative voltage generator coupled to the circuit and wherein the negative voltage generator is configured to generate a negative power supply voltage, and wherein the negative voltage generator comprises a charge pump circuit.

61. The circuit of claim 60, wherein the circuit comprises a single-pole, multi-throw RF switch.

62. The circuit of claim 60, wherein the circuit comprises a multi-pole, single-throw RF switch.

63. The circuit of claim 60, wherein the circuit comprises a multi-pole, multi-throw RF switch.

64. A circuit, comprising:

a) a first port means configured to output or receive a first signal;

b) a second port means configured to output or receive a second signal;

c) a common port means;

d) a first switch transistor grouping means having a first node coupled to the first port means and a second node coupled to the common port means, wherein the first switch transistor grouping means has a control node configured to be coupled to a first switch control signal;

e) a second switch transistor grouping means having a first node coupled to the second port means and a second node coupled to the common port means, wherein the second switch transistor grouping means has a control node configured to be coupled to a second switch control signal;

f) a first shunt transistor grouping means having a first node coupled to the first port means and a second node coupled to ground, wherein the first shunt transistor grouping means has a control node configured to be coupled to the second switch control signal; and

g) a second shunt transistor grouping means having a first node coupled to the second port means and a second node coupled to ground, wherein the second shunt transistor grouping means has a control node configured to be coupled to the first switch control signal.

65. The circuit of claim 64, wherein the first and second switch transistor grouping means comprise a single MOSFET, and wherein the first and second shunt transistor grouping means comprise a single MOSFET.

66. The circuit of claim 64, wherein the first and second switch transistor grouping means comprise a plurality of MOSFETs arranged in a stacked configuration, and wherein the first and second shunt transistor grouping means comprise a plurality of MOSFETs arranged in a stacked configuration.

67. The circuit of claim 64, wherein the first and the second switch transistor grouping means comprise a first number of MOSFETs arranged in a stacked configuration, and wherein the fist and second shunt transistor grouping means comprise a second number of MOSFETs arranged in a stacked configuration, and wherein the first number and the second number of MOSFETs differ.