Field-programmable gate array based accelerator system
First Claim
1. A system comprising:
- a Field Programmable Gate Array (FPGA) provided on a substrate;
a memory connected to the substrate and the FPGA;
an interface for connecting the FPGA to a computing device; and
a relevance-ranking algorithm for documents implemented at least in part by the FPGA, the FPGA configured to generate a result of the relevance-ranking algorithm based at least in part on the FPGA building an integral histogram based at least in part on feature values corresponding to one or more terms in one or more of the documents included in training data associated with the relevance-ranking algorithm.
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Abstract
Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and flexibility. The accelerator system may be used to implement a relevance-ranking algorithm, such as RankBoost, for a training process. The algorithm and related data structures may be organized to enable streaming data access and, thus, increase the training speed. The data may be compressed to enable the system and method to be operable with larger data sets. At least a portion of the approximated RankBoost algorithm may be implemented as a single instruction multiple data streams (SIMD) architecture with multiple processing engines (PEs) in the FPGA. Thus, large data sets can be loaded on memories associated with an FPGA to increase the speed of the relevance ranking algorithm.
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Citations
20 Claims
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1. A system comprising:
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a Field Programmable Gate Array (FPGA) provided on a substrate; a memory connected to the substrate and the FPGA; an interface for connecting the FPGA to a computing device; and a relevance-ranking algorithm for documents implemented at least in part by the FPGA, the FPGA configured to generate a result of the relevance-ranking algorithm based at least in part on the FPGA building an integral histogram based at least in part on feature values corresponding to one or more terms in one or more of the documents included in training data associated with the relevance-ranking algorithm. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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mapping data in one or more data structures to one or more memories associated with a Field Programmable Gate Array (FPGA), wherein at least a portion of the data includes training data associated with a relevance-ranking algorithm for documents; and learning the relevance ranking-algorithm based at least in part on logic of the FPGA building one or more integral histograms based at least in part on feature values associated with the training data corresponding to one or more terms of at least one of the documents. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A system comprising:
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a memory; and a Field Programmable Gate Array (FPGA) connected to the memory, the FPGA configured to learn a relevance-ranking algorithm for documents by processing engines (PEs) of the FPGA building integral histograms using training data associated with term-based feature values of the documents, wherein the term-based feature values are organized into bins that define at least in part a streaming memory access order for storing at least a portion of the training data in the memory for streaming memory access by each of the PEs for the building of the integral histograms. - View Dependent Claims (17, 18, 19, 20)
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Specification