Communications control bus and apparatus for controlling multiple electronic hardware devices
First Claim
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1. A communications control bus, the bus comprising:
- a) an Intelligent Master Base (IMB) slave CPU;
b) at least two registers;
c) a first three bit data connector for connecting the at least two registers, the connector permitting transmission of a three bit data signal between the at least two registers; and
d) a network interconnecting the at least two registers and the IMB slave CPU.
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Abstract
Disclosed is a communications control bus. The bus comprises an IMB slave CPU, at least two registers, and a three bit data connector, which connects the two registers. The connector permits transmission of a three bit data signal between the two registers. A network interconnects the two registers and the IMB slave CPU.
33 Citations
60 Claims
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1. A communications control bus, the bus comprising:
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a) an Intelligent Master Base (IMB) slave CPU; b) at least two registers; c) a first three bit data connector for connecting the at least two registers, the connector permitting transmission of a three bit data signal between the at least two registers; and d) a network interconnecting the at least two registers and the IMB slave CPU. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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Specification