Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain
First Claim
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1. An accelerator system, comprising:
- a plurality of processing cores, each processing core comprising;
a plurality of processing chains configured to perform parallel computations, each comprising a plurality of interconnected processing elements; and
a plurality of smart memory blocks configured to selectively store data based on an operation, each memory block accepting the output of one of the plurality of processing chains, wherein each smart memory block comprises;
a memory configured to store data elements; and
a filter configured to compare input data elements to a threshold and to store those elements in the memory only if the elements meet the threshold; and
at least one off-chip memory bank connected to each of the processing cores.
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Abstract
Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to store and process data, each memory block accepting the output of one of the plurality of processing chains. The cores communicate with at least one off-chip memory bank.
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Citations
11 Claims
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1. An accelerator system, comprising:
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a plurality of processing cores, each processing core comprising; a plurality of processing chains configured to perform parallel computations, each comprising a plurality of interconnected processing elements; and a plurality of smart memory blocks configured to selectively store data based on an operation, each memory block accepting the output of one of the plurality of processing chains, wherein each smart memory block comprises; a memory configured to store data elements; and a filter configured to compare input data elements to a threshold and to store those elements in the memory only if the elements meet the threshold; and at least one off-chip memory bank connected to each of the processing cores. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification