System and method for managing processor-in-memory (PIM) operations

• US 8,583,898 B2
• Filed: 06/12/2009
• Issued: 11/12/2013
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Greyzck, Terry D.
• Primary Examiner(s): Wong, Don
• Assistant Examiner(s): KABIR, MOHAMMAD H
• Application Number:
  US12/484,062
• Publication Number:
  US 20100318764A1
• Time in Patent Office: 1,614 Days
• Field of Search: 717/143
• US Class Current: 712/208
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3455 using stride

Abstract

A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for operations that are vectorizable. The vectorizable operations are examined to determine whether they should be executed at least in part in a vector atomic memory operation (AMO) functional unit attached to memory. If so, the compiled code includes vector AMO instructions.

Claims

1. A method performed by a computer system during compilation of program code for vectorizing an iterative loop of the program code for execution by a vector computer system having a plurality of processors connected to memory, wherein the memory includes one or more vector atomic memory operation (AMO) functional units and the processors include one or more vector functional units, the method comprising:

scanning the program code, wherein scanning includes determining whether an operation of the iterative loop is vectorizable;

if an operation is vectorizable, determining whether the operation should be executed using a vector AMO instruction in one of the vector AMO functional units;

if an operation is vectorizable and the operation should be executed using a vector AMO instruction in one of the vector AMO functional units, compiling at least a portion of the operation into a vector AMO instruction; and

if an operation is vectorizable and the operation should not be executed using a vector AMO instruction in one of the vector AMO functional units, compiling at least a portion of the operation to execute in one or more vector functional units of one or more processors.

2. The method of claim 1, wherein determining whether the operation should be executed using a vector AMO instruction in one of the vector AMO functional units is a function of memory transfer overhead.

3. The method of claim 1, wherein determining whether the operation should be executed using a vector AMO instruction in one of the vector AMO functional units is a function of computational speed difference between one or more of the vector functional units and one or more of the vector AMO functional units.

4. The method of claim 1, wherein the program code includes an array having an additional dimension depicting processor number and wherein determining whether the operation should be executed using a vector AMO instruction in one of the vector AMO functional units is a function of processor number.

5. The method of claim 1, wherein the vector atomic memory operation is performed in a memory controller.

6. A computer implemented method of compiling program code for execution by a vector computer system having a plurality of processors connected to memory, wherein the memory includes one or more vector atomic memory operation (AMO) functional units and the processors include one or more vector functional units, the method comprising:

a) scanning the program code for an operation that is vectorizable;

b) determining whether some portion of the vectorizable equation should be executed in the vector AMO functional unit; and

c) generating compiled code to replace the equation with vectorized machine executable code;

wherein, if a determination was made that some portion of the vectorizable equation should be executed in the vector AMO functional unit, the vectorized machine executable code includes vectorization code for performing a mathematical operation using one or more vector atomic memory operations; and

wherein, if a determination was made that some portion of the vectorizable equation should be not executed in the vector AMO functional unit, the vectorized machine executable code includes vectorization code for performing vector operations without using the vector AMO functional unit.

7. The method of claim 6, wherein the vector atomic memory operation is performed in a memory controller.

8. The method of claim 6, determining whether some portion of the vectorizable equation should be executed in the vector AMO functional unit includes determining whether an operation has recurring data points.

9. The method of claim 6, wherein determining whether some portion of the vectorizable equation should be executed in the vector AMO functional unit is a function of memory transfer overhead.

10. The method of claim 6, wherein determining whether some portion of the vectorizable equation should be executed in the vector AMO functional unit is a function of computational speed difference between one or more of the vector functional units and one or more of the vector AMO functional units.

11. The method of claim 6, wherein the program code includes an array having an additional dimension depicting processor number and wherein determining whether some portion of the vectorizable equation should be executed in the vector AMO functional unit is a function of processor number.

12. An article comprising a memory having instructions for controlling a computer to compile program code into code for execution by an vector atomic memory operation (AMO) functional unit and by a vector functional unit of a vector computer system, the instructions comprising instructions that:

identify a vectorizable equation within the program code;

identify a first portion of the vectorizable equation that should be executed using a vector AMO instruction in one of the vector AMO functional units;

output a vector AMO instruction to implement the first portion;

identify a second portion of the vectorizable equation that should be executed using a vector AMO instruction in one of the vector AMO functional units; and

output a vector instruction of a vector functional unit to implement the second portion.

13. The article of claim 12 wherein the identifying of the first portion is based on a function of memory transfer overhead.

14. The article of claim 12 wherein the identifying of the first portion is based on a function of computational speed difference between the vector AMO functional unit and the vector functional unit.

15. An article comprising a memory having instructions for controlling a computer to compile program code with an iterative loop into code for execution by an vector atomic memory operation (AMO) functional unit and by a vector functional unit of a processor, the instructions comprising instructions that:

scan program code to determine whether an operation is vectorizable;

if the operation is vectorizable, determine whether a portion of the operation should be executed using a vector AMO instruction in one of the vector AMO functional units;

if the portion of the operation should be executed using a vector AMO instruction in one of the vector AMO functional units, compile the portion of the operation to execute in a vector AMO functional unit; and

if the portion of operation should not be executed using a vector AMO instruction in one of the vector AMO functional units, compile the portion of the operation to execute in one or more vector functional units of one or more processors.

16. The article of claim 15, wherein determining whether the portion of the operation should be executed using a vector AMO instruction in one of the vector AMO functional units is a function of memory transfer overhead.

17. The article of claim 15, wherein determining whether the portion of the operation should be executed using a vector AMO instruction in one of the vector AMO functional units is a function of computational speed difference between one or more of the vector functional units and one or more of the vector AMO functional units.

18. The article of claim 15, wherein the program code includes an array having an additional dimension depicting processor number and wherein determining whether the portion of the operation should be executed using a vector AMO instruction in one of the vector AMO functional units is a function of processor number.