Planarization of a material system in a semiconductor device by using a non-selective in situ prepared slurry

• US 8,585,465 B2
• Filed: 12/16/2010
• Issued: 11/19/2013
• Est. Priority Date: 04/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Groschopf, Johannes, Hueselitz, Rico, Kitsche, Marco, Steffen, Katja
• Primary Examiner(s): NGUYEN, GEORGE BINH MINH
• Application Number:
  US12/969,969
• Publication Number:
  US 20110269381A1
• Time in Patent Office: 1,069 Days
• Field of Search: 451/5, 451/8, 451/36, 451/41, 451/54, 451 57- 58, 451/60, 451/65, 216/88, 216/89, 216/84, 438/692, 438/693, 438/8, 438/691, 252 791- 795
• US Class Current: 451/54
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

For complex CMP processes requiring the removal of different dielectric materials, possibly in the presence of a polysilicon material, a slurry material may be adapted at the point of use by selecting an appropriate pH value and avoiding agglomeration of the abrasive particles. The in situ preparation of the slurry material may also enable a highly dynamic adaptation of the removal conditions, for instance when exposing the polysilicon material of gate electrode structures in replacement gate approaches.

Claims

1. A method of planarizing a surface of a semiconductor device in the presence of a layer of silicon dioxide and a layer of silicon nitride, the method comprising:

providing a first solution in a manufacturing environment, said first solution having a first pH value and comprising abrasive particles, wherein a percentage of said abrasive particles is between 6 weight percent and 9 weight percent;

providing a second solution in said manufacturing environment, said second solution comprising an acid;

producing a slurry solution in said manufacturing environment from at least said first and second solutions, said slurry solution having a second pH value between 6.5 and 8; and

performing a planarization process in said manufacturing environment using said slurry solution produced in said manufacturing environment, wherein, when performing said planarization process using said slurry solution, a difference between a removal rate of said layer of silicon dioxide and a removal rate of said layer of silicon nitride solution is less than 10% of the removal range of said layer of silicon dioxide.

2. The method of claim 1, wherein said planarization process is performed in the presence of polysilicon.

3. The method of claim 1, wherein producing said slurry solution further comprises stabilizing said slurry solution so as to avoid agglomeration of abrasive particles at said second pH value.

4. The method of claim 3, wherein stabilizing said slurry solution comprises adding de-ionized water.

5. The method of claim 3, wherein stabilizing said slurry solution comprises adding a surfactant.

6. The method of claim 1, further comprising adjusting said difference between said removal rate of said layer of silicon dioxide and said removal rate of said layer of silicon nitride by dynamically varying said percentage of abrasive particles when producing said slurry solution.

7. The method of claim 6, further comprising obtaining a status signal when performing said planarization process and adjusting said difference between said removal rate of said layer of silicon dioxide and said removal rate of said layer of silicon nitride in correlation to said status signal.

8. The method of claim 1, further comprising forming said layer of silicon dioxide and said layer of silicon nitride above a gate electrode structure that comprises a semiconductor material and performing said planarization process so as to expose a surface of said semiconductor material.

9. A method of planarizing a surface of a semiconductor device in the presence of a layer of silicon dioxide and a layer of silicon nitride, the method comprising:

providing a first solution in a manufacturing environment, said first solution having a first pH value and comprising abrasive particles, wherein a percentage of said abrasive particles is between 6 weight percent and 9 weight percent;

providing a second solution in said manufacturing environment, said second solution comprising an acid;

producing a slurry solution in said manufacturing environment from at least said first and second solutions, said slurry solution having a second pH value between 7 and 8; and

performing a planarization process in said manufacturing environment using said slurry solution produced in said manufacturing environment while maintaining a concentration of abrasive particles within said slurry at a concentration level such that a ratio of a removal rate of said layer of silicon dioxide to a removal rate of said layer of silicon nitride falls within a range of 0.95-1.05.

10. The method of claim 9, wherein producing said slurry solution further comprises stabilizing said slurry solution so as to avoid agglomeration of abrasive particles at said second pH value.

11. The method of claim 10, wherein stabilizing said slurry solution comprises adding at least one of de-ionized water and a surfactant.

12. The method of claim 11, wherein at least said surfactant is added so as to further adjust a removal rate of said semiconductor material in said gate electrode structure.

13. The method of claim 9, wherein producing said slurry solution and said planarization process are performed in the same manufacturing environment.