Test point design for a high speed bus

• US 8,586,873 B2
• Filed: 02/23/2010
• Issued: 11/19/2013
• Est. Priority Date: 02/23/2010
• Status: Expired due to Fees

• Current Assignee: Flextronics America LLC (Flextronics International Limited)
• Original Assignee: Flextronics America LLC (Flextronics International Limited)
• Inventors: Wu, Leon
• Primary Examiner(s): Chen, Xiaoliang
• Application Number:
  US12/710,622
• Publication Number:
  US 20110203840A1
• Time in Patent Office: 1,365 Days
• Field of Search: 174/261, 174/255, 174/262, 174/264, 361/736, 361/780, 361/792, 361/794, 333/4, 333/34, 333/156
• US Class Current: 174/261
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 2203/162 Testing a finished product, e.g. heat cycle testing of solder joints
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths

Abstract

A circuit board includes a pair of differential signal lines and a pair of test point pads, one test point pad coupled to one of the signal lines and another of the test point pads coupled to another of the signal lines. The two test point pads are staggered relative to each other and the two signal lines. The circuit board includes a plurality of conductive layers and a plurality of insulating layers. The conductive layers can be etched into conductive patterns, or traces, for connecting the electronic components, which are soldered to the circuit board. The conductive layers may be selectively connected together by vias. One or more of the conductive layers may be a metal plane for providing a ground plane and/or a power plane. To minimize or eliminate the capacitance generated between the test point pad and an underlying ground plane and/or power plane, portions of the ground plane and/or the portion of the power plane directly aligned with each test point pad are removed.

Claims

1. A test point design comprising:

a. a circuit board comprising a plurality of layers including a power plane, a ground plane, and a dielectric plane between the power plane and the ground plane, the circuit board further comprises a differential pair of signal lines including a first signal line and a second signal line; and

b. a pair of test point pads including a first test point pad connected to the first signal line and a second test point pad connected to second signal line, wherein a first portion of the power plane and a first portion of the ground plane below the first test point pad are removed, and a first portion of the dielectric plane below the first test point is not removed, and a second portion of the power plane and a second portion of the ground plane below the second test point pad are removed, and a second portion of the dielectric plane below the second test point is not removed, wherein the first portions of the power plane and the ground plane that are removed, and the first portion of the dielectric plane that is not removed are the portions of the power plane, dielectric plane and the ground plane that are aligned underneath the first test point pad, and the second portions of the power plane and the ground plane that are removed, and the second portion of the dielectric plane that is not removed are the portions of the power plane, dielectric plane and the ground plane that are aligned underneath the second test point pad, and wherein the removed portions remain void of any material.

2. The test point design of claim 1 wherein the first test point pad and the second test point pad are staggered relative to the pair of signal lines.

3. The test point design of claim 2 wherein the first test point pad and the second test point pad are staggered such that a first perpendicular line between a center of the first test point pad and the first signal line is not aligned with a second perpendicular line between a center of the second test point pad and the second signal line.

4. The test point design of claim 2 wherein the pitch between the center of the first test point pad and the center of the second test point pad is about 65 millimeters.

5. The test point design of claim 2 wherein the pair of test point pads are staggered by a pitch sufficient to enable a first probe to contact the first test point pad and a second probe to contact the second test point pad concurrently.

6. The test point design of claim 1 wherein the differential signal lines are positioned adjacent to each other.

7. The test point design of claim 1 wherein a segment of the first signal line connected to the first test pad, a segment of the second signal line connected to the second test pad, the first test pad, and the second test pad are all positioned in a same plane.

8. The test point design of claim 1 wherein the first test point pad and the second test point pad are both positioned on an outer layer of the circuit board.

9. The test point design of claim 1 wherein the circuit board comprises a plurality of power planes, and the first portion and the second portion from one or more power planes nearest the first test point pad and the second test point pad are removed.

10. The test point design of claim 1 wherein the circuit board comprises a plurality of ground planes, and the first portion and the second portion from one or more ground planes nearest the first test point pad and the second test point pad are removed.

11. The test point design of claim 1 wherein the circuit board comprises a plurality of power planes and a plurality of ground planes, and the first portion and the second portion from one or more power planes and one or more ground planes nearest the first test point pad and the second test point pad are removed.