Semiconductor test chip device to mimic field thermal mini-cycles to assess reliability

• US 8,586,982 B2
• Filed: 08/25/2010
• Issued: 11/19/2013
• Est. Priority Date: 08/25/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: LaCroix, Luke D., Patel, Janak G., Slota, Peter Jr., Stone, David B.
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US12/862,844
• Publication Number:
  US 20120049874A1
• Time in Patent Office: 1,182 Days
• Field of Search: 257/48, 324/750.03, 324/750.06, 324/762.01, 324/762.03
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2875 related to heating

Abstract

A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.

Claims

1. A semiconductor test device comprising:

a plurality of layers, each of said layers comprising integrated circuit devices;

a plurality of heat generating structures, each of said heat generating structures being sized and positioned within said semiconductor test device to only heat a predetermined limited area of said layers;

a plurality of thermal monitors positioned within each of said plurality of layers; and

a control unit operatively connected to said heat generating structures and said thermal monitors.

2. The semiconductor test device according to claim 1, said control unit selectively activating a predetermined pattern of said heat generating structures to selectively create hot spots within said layers.

3. The semiconductor test device according to claim 1, said heat generating structures comprising:

at least one individually controllable power dissipation element; and

at least one transistor connected to said power dissipation element,

said transistor controlling whether said power dissipation element generates heat, and

said power dissipation element comprising one of a resistor and a transistor.

4. The semiconductor test device according to claim 1, each of said thermal monitors being sized and positioned within said semiconductor test device to only detect temperatures of a second predetermined limited area of said layers.

5. The semiconductor test device according to claim 4, said second predetermined area corresponding to said predetermined area, such that each of said heat generating structures has a corresponding thermal monitor.

6. The semiconductor test device according to claim 1, further comprising:

a plurality of second monitors positioned within each of said layers to detect one of electrical and mechanical failure,

wherein said control unit operatively connected to said plurality of second monitors.

7. A semiconductor test device comprising:

a plurality of conductive layers, each of said layers comprising integrated circuit devices;

a plurality of insulating layers between said conductive layers;

a plurality of heat generating structures positioned between said insulating layers and said conductive layers, each of said heat generating structures being sized and positioned to only heat a predetermined limited area of said plurality of layers;

a plurality of thermal monitors positioned within each of said layers; and

a control unit operatively connected to said heat generating structures and said thermal monitors.

8. The semiconductor test device according to claim 7, said control unit selectively activating a predetermined pattern of said heat generating structures to selectively create one of hot spots and hot zones within said layers.

9. The semiconductor test device according to claim 7, said heat generating structures comprising:

at least one individually controllable power dissipation element; and

at least one transistor connected to said power dissipation element,

said transistor controlling whether said power dissipation element generates heat, and

said power dissipation element comprising one of a resistor and a transistor.

10. The semiconductor test device according to claim 7, each of said thermal monitors being sized and positioned within said semiconductor test device to only detect temperatures of a second predetermined limited area of said layers.

11. The semiconductor test device according to claim 10, said second predetermined area corresponding to said predetermined area, such that each of said heat generating structures has a corresponding thermal monitor.

12. The semiconductor test device according to claim 7, further comprising:

a plurality of second monitors positioned within each of said layers to detect one of electrical and mechanical failure,

wherein said control unit operatively connected to said plurality of second monitors.

13. A semiconductor test device comprising:

a plurality of conductive layers, each of said layers comprising integrated circuit devices;

a plurality of insulating layers between said conductive layers;

a plurality of heat generating structures positioned between said insulating layers and said conductive layers, each of said heat generating structures being sized and positioned to only heat a predetermined limited area of said plurality of layers;

a plurality of thermal monitors positioned within each of said plurality of layers; and

a control unit operatively connected to said heat generating structures and said thermal monitors, said control unit individually cycling said heat generating structures on and off for multiple heat cycles, such that different areas of said layers are treated to different heat cycles.

14. The semiconductor test device according to claim 13, said control unit selectively activating a predetermined pattern of said heat generating structures to selectively create one of thermal hot spots and hot zones within said layers.

15. The semiconductor test device according to claim 13, said heat generating structures comprising:

at least one individually controllable power dissipation element; and

at least one transistor connected to said power dissipation element,

said transistor controlling whether said power dissipation element generates heat, and

said power dissipation element comprising one of a resistor and a transistor.

16. The semiconductor test device according to claim 13, each of said thermal monitors being sized and positioned within said semiconductor test device to only detect temperatures of a second predetermined limited area of said layers.

17. The semiconductor test device according to claim 16, said second predetermined area corresponding to said predetermined area, such that each of said heat generating structures has a corresponding thermal monitor.

18. The semiconductor test device according to claim 13, further comprising:

a plurality of second monitors positioned within each of said layers to detect one of electrical and mechanical failure,

wherein said control unit operatively connected to said plurality of second monitors.

19. The semiconductor test device according to claim 13, wherein said different areas of said layers reside in different locations on a single layer.

20. The semiconductor test device according to claim 13, wherein said different areas of said layers reside in different layers.