Monolithically integrated HEMT and current protection device

• US 8,587,033 B1
• Filed: 06/04/2012
• Issued: 11/19/2013
• Est. Priority Date: 06/04/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Rieger, Walter, Hberlen, Oliver
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US13/487,795
• Publication Number:
  US 20130320952A1
• Time in Patent Office: 533 Days
• Field of Search: 257/191, 257/192, 257/194, 257/195, 257/E29.246, 257/E21.403, 257/E21.407
• US Class Current: 257/195
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A transistor device includes a high electron mobility field effect transistor (HEMT) and a protection device. The HEMT has a source, a drain and a gate. The HEMT switches on and conducts current from the source to the drain when a voltage applied to the gate exceeds a threshold voltage of the HEMT. The protection device is monolithically integrated with the HEMT so that the protection device shares the source and the drain with the HEMT and further includes a gate electrically connected to the source. The protection device conducts current from the drain to the source when the HEMT is switched off and a reverse voltage between the source and the drain exceeds a threshold voltage of the protection device. The protection device has a lower threshold voltage than the difference of the threshold voltage of the HEMT and a gate voltage used to turn off the HEMT.

Claims

1. A transistor device, comprising:

a high electron mobility field effect transistor (HEMT) having a source, a drain, a gate, and a first insulator separating the gate from a compound semiconductor body of the transistor device, the HEMT operable to switch on and conduct current from the source to the drain when a voltage applied to the gate exceeds a threshold voltage of the HEMT; and

a protection device monolithically integrated with the HEMT so that the protection device shares the source and the drain with the HEMT and further comprises a gate electrically connected to the source and a second insulator separating the gate of the protection device from the compound semiconductor body, the protection device operable to conduct current from the drain to the source when the HEMT is switched off and a reverse voltage between the source and the drain exceeds a threshold voltage of the protection device, the threshold voltage of the protection device being less than the difference of the threshold voltage of the HEMT and a gate voltage used to turn off the HEMT,

wherein the first insulator is thinner under the gate of the HEMT than the second insulator under the gate of the protection device.

2. The transistor device of claim 1, wherein the threshold voltage of the protection device is greater than 0 V and less than 1.5V.

3. The transistor device of claim 1, wherein the HEMT is a normally-off HEMT.

4. A DC-to-DC converter, comprising:

a high-side transistor for coupling to a load;

a low-side high electron mobility field effect transistor (HEMT) for coupling to the load; and

a protection device monolithically integrated with the low-side HEMT in a compound semiconductor body so that the protection device shares a source and a drain with the low-side HEMT and further comprises a gate electrically connected to the source, the protection device operable to conduct current between the drain and the source when the low-side HEMT is switched off, the high-side HEMT is switched off and a reverse voltage between the source and the drain exceeds a threshold voltage of the protection device, the threshold voltage of the protection device being less than the difference of the threshold voltage of the HEMT and a gate voltage used to turn off the HEMT,

wherein a first insulator separating a gate of the HEMT from the compound semiconductor body is thinner than a second insulator separating the gate of the protection device from the compound semiconductor body.

5. The DC-to-DC converter of claim 4, wherein the threshold voltage of the protection device is greater than 0 V and less than 1.5V.

6. A semiconductor device, comprising:

a compound semiconductor body;

a high electron mobility field effect transistor (HEMT) comprising a source extending into the compound semiconductor body, a drain spaced apart from the source and extending into the compound semiconductor body, a gate disposed in a first trench extending into the compound semiconductor body, and a first insulator separating the gate from the compound semiconductor body in the first trench;

a protection device comprising a source common with the source of the HEMT, a drain common with the drain of the HEMT, a gate disposed in a second trench extending into the compound semiconductor body and electrically connected to the source, and a second insulator separating the gate of the protection device from the compound semiconductor body in the second trench; and

wherein at least one of the first insulator is thinner in the first trench than the second insulator in the second trench and the first trench extends deeper into the compound semiconductor body than the second trench.

7. The semiconductor device of claim 6, wherein the first insulator and the second insulator are formed from the same aluminum oxide layer.

8. The semiconductor device of claim 6, wherein the gate of the HEMT and the gate of the protection device each comprise p-type GaN, and wherein at least one of a thickness and a doping concentration of the p-type GaN gate of the HEMT is different than that of the p-type GaN gate of the protection device.

9. The semiconductor device of claim 6, wherein the gate of the HEMT and the gate of the protection device each comprise undoped GaN, and wherein at least one of a thickness and a width of the undoped GaN gate of the HEMT is different than that of the undoped GaN gate of the protection device.

10. The semiconductor device of claim 9, further comprising a first gate metal in contact with the undoped GaN gate of the HEMT and a second gate metal in contact with the undoped GaN gate of the protection device, and wherein the first gate metal and the second gate metal comprise different materials, have different thicknesses, or both.

11. The semiconductor device of claim 6, wherein a two-dimensional electron gas arises in the compound semiconductor body between the source and the drain, wherein the two-dimensional electron gas is interrupted below the gate of the HEMT when a voltage applied to the gate of the HEMT is below a threshold voltage of the HEMT, and wherein the two-dimensional electron gas is interrupted below the gate of the protection device when a voltage applied to the gate of the protection device is below a threshold voltage of the protection device.

12. The semiconductor device of claim 11, further comprising an implanted region which disrupts the two-dimensional electron gas in the compound semiconductor body between the HEMT and the protection device.

13. The semiconductor device of claim 6, wherein the HEMT is a normally-off HEMT.

14. The semiconductor device of claim 6, wherein the compound semiconductor body comprises an AlGaN layer disposed on a GaN layer, a two-dimensional electron gas arises near the interface between the AlGaN layer and the GaN layer, and a thickness of the AlGaN layer is different for the HEMT than for the protection device.

15. A method of manufacturing a semiconductor device, comprising:

forming a high electron mobility field effect transistor (HEMT) in a compound semiconductor body, the HEMT comprising a source extending into the compound semiconductor body, a drain spaced apart from the source and extending into the compound semiconductor body, a gate disposed in a first trench extending into the compound semiconductor body, and a first insulator separating the gate from the compound semiconductor body in the first trench; and

monolithically integrating a protection device with the HEMT so that the protection device has a source common with the source of the HEMT, a drain common with the drain of the HEMT, a gate disposed in a second trench extending into the compound semiconductor body and electrically connected to the source, a second insulator separating the gate of the protection device from the compound semiconductor body in the second trench, and at least one of the first insulator is thinner in the first trench than the second insulator in the second trench and the first trench extends deeper into the compound semiconductor body than the second trench.

16. The method of claim 15, wherein the HEMT is formed while a region of the compound semiconductor body allocated for the protection device is protected and the protection device is formed at a different time while a different region of the compound semiconductor body allocated for the HEMT is protected so that the first insulator is formed thinner in the first trench than the second insulator in the second trench.

17. The method of claim 16, wherein the first insulator and the second insulator are formed from the same aluminum oxide layer deposited over both regions of the compound semiconductor body.

18. The method of claim 15, wherein the HEMT is formed while a region of the compound semiconductor body allocated for the protection device is protected and the protection device is formed at a different time while a different region of the compound semiconductor body allocated for the HEMT is protected so that the first trench is etched deeper into the compound semiconductor body than the second trench.

19. The method of claim 15, wherein the HEMT is formed while a region of the compound semiconductor body allocated for the protection device is protected and the protection device is formed at a different time while a different region of the compound semiconductor body allocated for the HEMT is protected so that the first insulator is formed thinner in the first trench than the second insulator in the second trench and the first trench is etched deeper into the compound semiconductor body than the second trench.

20. The method of claim 19, wherein the first insulator and the second insulator are formed from the same aluminum oxide layer deposited over both regions of the compound semiconductor body.

21. The method of claim 15, wherein the first insulator in the first trench and the second insulator in the second trench are formed by selectively depositing a contiguous dielectric material on the compound semiconductor body that is thinner in the first trench and thicker in the second trench.

22. The method of claim 15, wherein the first and second trenches are formed by etching the second trench and part of the first trench into the compound semiconductor body at the same time and protecting the second trench while the first trench is etched deeper into the compound semiconductor body.

23. The method of claim 15, wherein the gate of the HEMT and the gate of the protection device both comprise p-type GaN, and wherein at least one of a thickness and a doping concentration of the p-type GaN gate of the HEMT is different than that of the p-type GaN gate of the protection device.

24. The method of claim 15, wherein the gate of the HEMT and the gate of the protection device both comprise undoped GaN, and wherein at least one of a thickness and a width of the undoped GaN gate of the HEMT is different than that of the undoped GaN gate of the protection device.

25. The method of claim 24, further comprising forming a first gate metal of a first material in contact with the undoped GaN gate of the HEMT and a second gate metal of a second material different than the first material in contact with the undoped GaN gate of the protection device, and wherein the first gate metal and the second gate metal comprise different materials, have different thicknesses, or both.