Integrated circuit and fabricating method thereof

• US 8,587,078 B2
• Filed: 04/06/2010
• Issued: 11/19/2013
• Est. Priority Date: 04/06/2010
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Huang, Chien-Hsin, Chen, Li-Che, Wang, Ming-I, Lan, Bang-Chiang, Tan, Tzung-Han, Wu, Hui-Min, Su, Tzung-I
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Gupta, Raj R
• Application Number:
  US12/754,610
• Publication Number:
  US 20110241137A1
• Time in Patent Office: 1,323 Days
• Field of Search: 257/254, 257/416, 257/419
• US Class Current: 257/419
• CPC Class Codes: B81B 2201/0257 Microphones or microspeakers
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence

Abstract

A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.

Claims

1. An integrated circuit, comprising:

a silicon substrate with a logical circuit region and a micro electromechanical system (MEMS) region;

a metal oxide semiconductor device disposed on the logical circuit region of the silicon substrate;

an interconnecting structure disposed above the silicon substrate and electrically connected with the metal oxide semiconductor device, the interconnecting structure comprises a plurality of dielectric layers, wherein each dielectric layer filled with the at least a conductive material; and

a MEMS diaphragm disposed between any two adjacent dielectric layers located on the MEMS region, wherein the dielectric layer under the MEMS diaphragm has a plurality of first openings exposing corresponding conductive materials, the MEMS diaphragm comprising;

a bottom insulating layer covering sidewalls of the first opening and having at least a first trench;

a first electrode layer disposed on the bottom insulating layer and filling into the first trench to electrically connect with the corresponding conductive materials; and

a top insulating layer disposed on the first electrode layer.

2. The integrated circuit as claimed in claim 1, wherein the silicon substrate has a plurality of holes communicating to a vibration cavity, and the interconnecting structure has a voice entrance located above the vibration cavity and exposing a portion of the MEMS diaphragm.

3. The integrated circuit as claimed in claim 1, wherein the interconnecting structure further comprises a guard-ring disposed under the MEMS diaphragm and surrounding the vibration cavity.

4. The integrated circuit as claimed in claim 1, wherein the MEMS diaphragm is flat or curviform.

5. The integrated circuit as claimed in claim 1, further comprising a second electrode layer electrically connecting to the interconnecting structure and disposed above the MEMS diaphragm so as to form a vibration cavity therebetween, the second electrode layer has a plurality of holes communicating to the vibration cavity and the MEMS diaphragm exposed by the silicon substrate.

6. The integrated circuit as claimed in claim 5, wherein the interconnecting structure further comprises a guard-ring disposed above the MEMS diaphragm and surrounding the vibration cavity.

7. An integrated circuit, comprising:

a silicon substrate;

an interconnecting structure disposed above the silicon substrate and comprising a plurality of dielectric layers, wherein each dielectric layer filled with the at least a conductive material; and

a micro electromechanical system (MEMS) diaphragm disposed between any two adjacent dielectric layers, wherein the dielectric layer under the MEMS diaphragm has a plurality of first openings exposing corresponding conductive materials, the MEMS diaphragm comprising;

a bottom insulating layer covering sidewalls of the first opening and having at least a first trench;

a first electrode layer disposed on the bottom insulating layer and filling into the first trench to electrically connect with the corresponding conductive materials; and

a top insulating layer disposed on the first electrode layer.

8. The integrated circuit as claimed in claim 7, wherein the silicon substrate has a plurality of holes communicating to a vibration cavity and the interconnecting structure has a voice entrance located above the vibration cavity and exposing a portion of the MEMS diaphragm.

9. The integrated circuit as claimed in claim 7, wherein the interconnecting structure further comprises a guard-ring disposed under the MEMS diaphragm and surrounding the vibration cavity.

10. The integrated circuit as claimed in claim 7, wherein the MEMS diaphragm is flat or curviform.

11. The integrated circuit as claimed in claim 7, further comprising a second electrode layer electrically connecting to the interconnecting structure and disposed above the MEMS diaphragm so as to form a vibration cavity therebetween, the second electrode layer has a plurality of holes communicating to the vibration cavity, the MEMS diaphragm exposed by the silicon substrate.

12. The integrated circuit as claimed in claim 11, wherein the interconnecting structure further comprises a guard-ring disposed above the MEMS diaphragm and surrounding the vibration cavity.

13. A method for fabricating an integrated circuit, comprising:

providing a silicon substrate with a logical circuit region and a micro electromechanical system (MEMS) region;

forming a metal oxide semiconductor device on the logical circuit region of the conductive substrate;

forming an interconnecting structure electrically connecting to the metal oxide semiconductor device and comprising a plurality of dielectric layers above the silicon substrate, each dielectric layer filled with the at least a conductive material;

forming a MEMS diaphragm between any two adjacent dielectric layers of the interconnecting structure on the MEMS region, wherein the steps of forming the MEMS diaphragm comprising;

forming a plurality of first openings in any dielectric layer of the interconnecting structure to expose the corresponding conductive materials;

forming a bottom insulating layer on the dielectric layer to fill into the first openings;

removing a portion of the bottom insulating layer located on the bottom of the first openings to form at least a first trench exposing corresponding at least a portion of one of the conductive materials;

forming a first electrode layer on the bottom insulating layer to fill into the first trench and electrically connect to the corresponding conductive materials; and

forming a top insulating layer to cover the first electrode layer.

14. The method as claimed in claim 13, further comprising a step of removing a portion of the dielectric layer positioned above the MEMS diaphragm to form a voice entrance exposing the MEMS diaphragm.

15. The method as claimed in claim 13, further comprising the step of filling at least one of the conductive materials into one of the dielectric layers disposed above the MEMS diaphragm during the steps of forming the interconnecting structure.

16. The method as claimed in claim 13, further comprising the step of forming a plurality of second openings within the dielectric layer having the first openings before forming the MEMS diaphragm, wherein the MEMS diaphragm filling into the second openings.

17. The method as claimed in claim 13, further comprising:

removing a portion of the MEMS region of the silicon substrate to form a plurality of holes for exposing a portion of the dielectric layers under the MEMS diaphragm; and

removing the portion of the dielectric layers under the MEMS diaphragm through the holes to form a vibration cavity between the second electrode layer and the MEMS diaphragm.

18. The method as claimed in claim 17, further comprising the step of forming a guard-ring surrounding a portion of the dielectric layer predetermined being formed the vibration cavity on the MEMS region of the silicon substrate during the steps of forming the interconnecting structure.

19. The method as claimed in claim 13, further comprising:

forming a second electrode layer electrically connecting to the interconnecting structure above the MEMS diaphragm;

removing a portion of the second electrode layer to form a plurality of holes exposing a portion of the dielectric layers formed above the MEMS diaphragm;

removing the portion of the dielectric layers above the MEMS diaphragm through the holes to form a vibration cavity between the second electrode layer and the MEMS diaphragm; and

removing a portion of the MEMS region of the silicon substrate and a portion of the dielectric layers under the MEMS diaphragm to form a voice entrance exposing a portion of the MEMS diaphragm.

20. The method as claimed in claim 19, further comprising the step of forming a guard-ring surrounding a portion of the dielectric layer predetermined being formed the vibration cavity on the MEMS region of the silicon substrate during the steps of forming the interconnecting structure.