Vertical system integration

• US 8,587,102 B2
• Filed: 05/09/2008
• Issued: 11/19/2013
• Est. Priority Date: 08/08/2002
• Status: Expired due to Fees

• Current Assignee: Glenn J. Leedy
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J
• Primary Examiner(s): LUKE, DANIEL M
• Application Number:
  US12/118,582
• Publication Number:
  US 20080237591A1
• Time in Patent Office: 2,020 Days
• Field of Search: 257/678, 257/777, 257/48
• US Class Current: 257/678
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/118 : Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1463 : Pixel isolation structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 29/40114 : the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 : Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04W 4/80 : Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 : DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Claims

1. A stacked integrated circuit comprising:

a first circuit layer; and

a second circuit layer overlying the first circuit layer,

wherein at least one of the first and second circuit layers comprises at least one integrated circuit; and

at least one interconnection between the first circuit layer and the second circuit layer, passing vertically through the at least one integrated circuit;

wherein at least one of the first and second circuit layers is selected from a stock of a plurality of different interoperable, previously-fabricated circuit layers.

2. The stacked integrated circuit of claim 1, wherein the first and second circuit layer and the second circuit layer each comprise at least one of the following:

a microprocessor, PLD or FPGA circuitry, a passive device array, a DSP, a SERDES, I/O circuitry, memory, and a graphics processor.

3. The stacked integrated circuit of claim 1, wherein the first and second circuit layers each comprise logic circuitry, and wherein at least partial logic circuit redundancy exists between the first and second circuit layers.

4. The stacked integrated circuit of claim 1, comprising at least a third circuit layers, each of the first, second and third circuit layers being either a memory layer or a PLD or FPGA circuit layer.

5. The stacked integrated circuit of claim 4, comprising at least a fourth circuit layer, wherein the circuit layers include a plurality of memory layers and a plurality of PLD or FPGA circuit layers.

6. The stacked integrated circuit of claim 1, wherein the stacked integrated circuit is provided with wireless interconnection capability.

7. The stacked integrated circuit of claim 1, comprising one or more additional circuit layers, wherein all of the circuit layers are bonded together such that no circuitry of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit.

8. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises electronic circuitry.

9. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises optical circuitry.

10. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises a MEMS device.

11. The stacked integrated circuit of claim 1, comprising integrated circuit devices fabricated on a backside of one or more of the first and second circuit layers.

12. The stacked integrated circuit of claim 11, wherein the integrated circuit devices comprise at least one of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

13. The stacked integrated circuit of claim 11, wherein the integrated circuit devices comprise at least two of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

14. The stacked integrated circuit of claim 11, wherein the integrated circuit devices comprise all of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

15. The stacked integrated circuit of claim 1, wherein the stacked integrated circuit comprises at least two of the following types of circuit layers:

electronic, optical and MEMS circuit layers.

16. The stacked integrated circuit of claim 1, wherein a dielectric layer is deposited on a backside of one or more of the first circuit layer and the second circuit layer to enhance electrical isolation of an underlying semiconductor device layer.

17. The stacked integrated circuit of claim 1, wherein integrated circuit device fabrication is performed on a backside of one or more of the first and second circuit layers to complete fabrication of integrated circuit devices partially formed on a front side of the one or more of the first and second circuit layers.

18. The stacked integrated circuit of claim 1, wherein integrated circuit fabrication is performed on a backside of one or more the circuit layer and the second circuit layer to fabricate one or more layer memory layers.

19. The stacked integrated circuit of claim 18, wherein the one or more memory layers comprise at least one of MRAM, PRAM, ferroelectric and dendritic memory.

20. The stacked integrated circuit of claim 1, wherein the first circuit layer and the second circuit layer are bonded using bonding layers made from two or more metal films, one of which has a lower melting point and which will diffuse with an immediately adjacent film.

21. The stacked integrated circuit of claim 20, wherein bonding layers form a diffused metal film having a higher melting point than the lower melting point metal film.

22. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises a programmable tester for testing of the stacked integrated circuit during burn-in or during its useful life.

23. The stacked integrated circuit of claim 1, wherein the first and second circuit layer comprises surfaces at least some of which have circuitry formed thereon, wherein all surfaces of the first circuit layer and the second circuit layer with circuitry formed thereon are internal to the stacked integrated circuit, whereby the stacked integrated circuit is its own packaging.

24. The stacked integrated circuit of claim 23, comprising a bonding layer for bonding together the first circuit layer and the second circuit layer, wherein the bonding layer forms a hermetic seal.

25. The stacked integrated circuit of claim 1, comprising a plurality of further circuit layers wherein two or more circuit layers have similar functioning circuitry in a vertical overlapping position.

26. The stacked integrated circuit of claim 1, comprising circuitry on the first circuit layer and the second layer, wherein the circuitry on the first circuit layer and the second circuit layer is reconfigurable by the use of vertical interconnections between the first circuit layer and the second circuit layer.

27. The stacked integrated circuit of claim 1, comprising one or more vertical interconnections between the first circuit layer and the second circuit layer having cross-sectional areas that are at least two times larger than any horizontal signal interconnection on either the first circuit layer or the second circuit layer.

28. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer is not designed specifically for the stacked integrated circuit.

29. The stacked integrated circuit of claim 1, wherein the stacked integrated circuit performs an application-specific that is derived from a choice and quantity of circuit layers from among previously fabricated, non-application-specific circuit layers.

30. The stacked integrated circuit of claim 1, wherein one or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are free-standing.

31. The stacked integrated circuit of claim 1, wherein one or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are without the mechanical support of a dielectric layer.

32. The stacked integrated circuit of claim 1, comprising circuitry on at least one of the first circuit layer and the second circuit layer, and interconnections on a backside of the at least one of the first circuit layer and the second circuit layer, wherein interconnections of circuitry on the at least one of the first circuit layer and the second circuit layer are changed by the interconnections on the backside of the at least one of the first circuit layer and the second circuit layer.

33. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises one or more transistor gates that are back biased by forming a contact on a backside of the at least one of the first circuit layer and the second circuit layer, opposite the one or more transistor gates.

34. The stacked integrated circuit of claim 1, comprising I/O drivers for the stacked integrated circuit, wherein the I/O drivers are physically stored on a separate circuit layer or on a backside of one of the first circuit layer and the second circuit layer.

35. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises a dielectric layer that has been predominately removed, leaving free-standing metal horizontal and vertical interconnections.

36. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises a predominately free-standing RF antenna.

37. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises a MEMS device.

38. The stacked integrated circuit of claim 37, wherein the first circuit layer comprises a MEMS device.

39. The stacked integrated circuit of claim 37, comprising another circuit layer, wherein the MEMS device is fabricated as part of the at least one of the first circuit layer and the second circuit layer after bonding of the at least one of the first circuit layer and the second circuit layer to said another circuit layer.

40. The stacked integrated circuit of claim 1, wherein the first and second circuit layers together comprise an optical circuit layer that couples signals into an electronic circuit layer.

41. The stacked integrated circuit of claim 1, wherein one of the first circuit layer and the second circuit layer comprises a generically programmable automatic testing circuit layer for testing another one of the first circuit layer and the second circuit layer of the stacked integrated circuit.

42. The stacked integrated circuit of claim 1, wherein the first circuit layer and the second circuit layer comprise redundant circuits interconnected by an interconnection wire, wherein an interconnection wire length between the redundant circuits is approximately equal to or less than a thickness of the stacked integrated circuit.

43. The stacked integrated circuit of claim 1, comprising a plurality of circuit layers including the first and second circuit layers, wherein the plurality of circuit layers comprise:

wireless circuitry for creating multiple data transmission paths between a plurality of stacked ICs, and

means for changing one or more wireless data transmission paths between any two stacked ICs as needed.

44. The stacked integrated circuit of claim 1, comprising a plurality of circuit layers including the first and second circuit layers, wherein the plurality of circuit layers comprise a plurality of wireless circuits configured to create a plurality of data transmission paths.

45. The stacked integrated circuit of claim 1, wherein at least one of the first circuit layer and the second circuit layer comprises circuitry for performing full-wafer test and burn-in.

46. The stacked integrated circuit of claim 1, comprising a plurality of circuit layers including the first and second circuit layers, wherein the plurality of circuit layers comprises memory control logic and memory circuit layers, and wherein at least one of the plurality of circuit layers comprises memory control logic circuitry enabling reconfiguration of the memory circuit layers of the stacked integrated circuit.

47. The stacked integrated circuit of claim 1, comprising a plurality of circuit layers including the first and second circuit layers, wherein the plurality of circuit layers together comprise memory control logic and memory circuit layers, and wherein at least one of the plurality of circuit layers comprises memory control logic circuitry enabling the use of a variable amount of a memory capacity of the stacked integrated circuit.

48. The stacked integrated circuit of claim 1, comprising a credit-card-shaped enclosure enclosing the stacked integrated circuit.

49. The stacked integrated circuit of claim 1, comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein the plurality of circuit layers together comprise a plurality of sensor devices and processing electronics coupled to the sensor devices, wherein the sensor devices are separated from and overlie the processing electronics coupled to the sensor devices.

50. The stacked integrated circuit of claim 1 wherein the stacked integrated circuit is a stacked programmable logic device comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein the plurality of circuit layers comprise at least one each of a programmable gate circuit layer, a routing circuit layer and a memory circuit layer.

51. The stacked integrated circuit of claim 1 wherein the stacked integrated circuit is a stacked programmable logic device comprising a plurality of circuit layers including the first circuit and the second circuit layer, wherein at least one circuit layer of the plurality of circuit layers comprises automatic test electronics.

52. The stacked integrated circuit of claim 1, comprising a plurality of circuit layers including the first and second circuit layers, wherein the plurality of circuit layers together comprise a plurality of processors, further comprising a non-blocking cross bar configured to interconnect the plurality of processors, wherein the non-blocking cross bar is integrated onto one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit.

53. The stacked integrated circuit of claim 1, wherein one or of the first circuit layer and the second circuit layer comprises analog circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the analog circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit.

54. The stacked integrated circuit of claim 1, wherein one or more of the first circuit layer and the second circuit layer comprises passive circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the passive circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit.

55. The stacked integrated circuit of claim 1, wherein the at least one integrated circuit comprises a single crystal semiconductor substrate, and wherein said one interconnection passes through and is insulated from said single crystal semiconductor substrate.

56. The stacked integrated circuit of claim 1, comprising a plurality of interconnections passing through the at least one integrated circuit, wherein at least one of the plurality of interconnections is a redundant interconnection.

115. The stacked integrated circuit of claim 1, wherein at least two of the following:

the first circuit layer and the second circuit layer each comprise at least one of a microprocessor, PLD or FPGA circuitry, a passive device array, a DSP, a SERDES, I/O circuitry, memory, and a graphics processor;

the stacked integrated circuit comprises at least partial logic circuit redundancy between different layers;

the stacked integrated circuit comprises at least three layers, each of the three layers being either a memory layer or a PLD or FPGA circuit layer;

the stacked integrated circuit is provided with wireless interconnection capability;

the stacked integrated circuit comprises a plurality of circuit layers bonded together such that no circuitry of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit;

at least one of the first circuit layer and second circuit layer comprises electronic circuitry;

at least one of the first circuit layer and second circuit layer comprises optical circuitry;

at least one of the first circuit layer and second circuit layer comprises a MEMS device;

the stacked integrated circuit comprises integrated circuit devices fabricated on the backside of one or more circuit layers;

the stacked integrated circuit comprises a plurality of circuit layers including at least two of a group consisting of electronic, optical and MEMS circuit layers;

the stacked integrated circuit comprises integrated circuit devices fabricated on the backside of one or more circuit layers;

a dielectric layer is deposited on the backside of one or more of the first circuit layer and the second circuit layer to enhance electrical isolation of an underlying semiconductor device layer;

integrated circuit device fabrication is performed on the backside of one or more circuit layers to complete the fabrication of integrated circuit devices partially formed on the front side of the one or more circuit layers;

integrated circuit fabrication is performed on the backside of one or more of the first circuit layer and the second circuit layer to fabricate one or more memory layers;

the first circuit layer and the second circuit layer are bonded using bonding layers made from two or more metal films, one of which has a lower melting point and which will diffuse with an immediately adjacent film;

at least one of the first circuit layer and the second circuit layer comprises a programmable tester for testing of the stacked integrated circuit during bum-in or during its useful life;

all surfaces of the first circuit layer and the second circuit layer with circuitry thereon are internal to the stacked integrated circuit whereby the stacked integrated circuit is its own packaging;

the stacked integrated circuit comprises a plurality of circuit layers wherein two or more circuit layers have similar functioning circuitry in a vertical overlapping position;

circuitry is formed on the first circuit layer and the second circuit layer, the circuitry on the first circuit layer and the second circuit layer being reconfigurable by the use of vertical interconnections between the first circuit layer and the second circuit layer;

the stacked integrated circuit comprises one or more vertical interconnections between the first circuit layer and the second circuit layer having cross-sectional areas that are at least two times larger than any horizontal signal interconnection;

some of the first circuit layer and the second circuit layer are not designed specifically for the particular stacked integrated circuit;

an application-specific function of the stacked integrated circuit is derived from the choice and quantity of circuit layers from previously fabricated, non-application-specific circuit layers;

or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are free-standing;

or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are without the mechanical support of a dielectric;

interconnections of circuitry on at least one of the first circuit layer and the second circuit layer are changed by interconnections on the backside of the circuit layer;

one or more transistor gates of at least one circuit layer is back biased by forming a contact on the backside of the at least one circuit layer opposite the one or more transistor gates;

I/O drivers for the stacked integrated circuit are physically on a separate circuit layer or on the backside of one of the first circuit layer and the second circuit layer;

in one of the first circuit layer and the second circuit layer dielectric has been predominately removed leaving free-standing metal horizontal and vertical interconnections;

the first circuit layer and the second circuit layer contains a predominately free-standing RE antenna;

one of the first circuit layer and the second circuit layer comprises a MEMS device;

one optical circuit layer couples signals into an electronic circuit layer;

one of the first circuit layer and the second circuit layer comprises a generically programmable automatic testing circuit layer for testing one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers with redundant circuits wherein an interconnection wire length between redundant circuits is approximately equal to or less than a thickness of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers including wireless circuitry for creating multiple data transmission paths between a plurality of stacked ICs, and means for changing one or more wireless data transmission paths between any two stacked ICs as needed;

the stacked integrated circuit comprises a plurality of circuit layers including a plurality of wireless circuits wherein the wireless circuits are used to create a plurality of data transmission paths;

the stacked integrated circuit comprises circuitry for performing full-wafer test and burn-in;

the stacked integrated circuit comprises memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling reconfiguration of the memory circuit layers of the stacked integrated circuit;

the stacked integrated circuit comprises memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling the use of a variable amount of the memory of the stacked integrated circuit;

the stacked integrated circuit comprises a credit-card-shaped enclosure enclosing the stacked integrated circuit;

the stacked integrated circuit comprises a sensing device with sensor devices separated and overlying processing electronics of the sensor devices;

the stacked integrated circuit comprises a stacked programmable logic device having a plurality of circuit layers wherein there is at least one each of a programmable gate circuit layer, a routing circuit layer and a memory circuit layer;

the stacked integrated circuit comprises a stacked programmable logic device having a plurality of circuit layers wherein there is at least one circuit layer comprising automatic test electronics;

the stacked integrated circuit comprises a plurality of circuit layers with processors thereon wherein a non-blocking cross bar interconnects the processors and is integrated onto the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers wherein one or more of the first circuit layer and the second circuit layer comprises analog circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the analog circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers wherein one or more of the first circuit layer and the second circuit layer comprises passive circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the passive circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the at least one integrated circuit comprises a single crystal semiconductor substrate, and wherein said one interconnection passes through and is insulated from said single crystal semiconductor substrate;

the stacked integrated circuit comprises a plurality of interconnections passing through the at least one integrated circuit, wherein at least one of the plurality of interconnections is a redundant interconnection.

116. The stacked integrated circuit of claim 1, wherein at least three of the following:

the first circuit layer and the second circuit layer each comprise at least one of a microprocessor, PLD or FPGA circuitry, a passive device array, a DSP, a SERDES, I/O circuitry, memory, and a graphics processor;

the stacked integrated circuit comprises at least partial logic circuit redundancy between different layers;

the stacked integrated circuit comprises at least three layers, each of the three layers being either a memory layer or a PLD or FPGA circuit layer;

the stacked integrated circuit is provided with wireless interconnection capability;

the stacked integrated circuit comprises a plurality of circuit layers bonded together such that no circuitry of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit;

at least one of the first circuit layer and second circuit layer comprises electronic circuitry;

at least one of the first circuit layer and second circuit layer comprises optical circuitry;

at least one of the first circuit layer and second circuit layer comprises a MEMS device;

the stacked integrated circuit comprises integrated circuit devices fabricated on the backside of one or more circuit layers;

the stacked integrated circuit comprises a plurality of circuit layers including at least two of a group consisting of electronic, optical and MEMS circuit layers;

the stacked integrated circuit comprises integrated circuit devices fabricated on the backside of one or more circuit layers;

a dielectric layer is deposited on the backside of one or more of the first circuit layer and the second circuit layer to enhance electrical isolation of an underlying semiconductor device layer;

integrated circuit device fabrication is performed on the backside of one or more circuit layers to complete the fabrication of integrated circuit devices partially formed on the front side of the one or more circuit layers;

integrated circuit fabrication is performed on the backside of one or more of the first circuit layer and the second circuit layer to fabricate memory layers;

the first circuit layer and the second circuit layer are bonded using bonding layers made from two or more metal films, one of which has a lower melting point and which will diffuse with an immediately adjacent film;

at least one of the first circuit layer and the second circuit layer comprises a programmable tester for testing of the stacked integrated circuit during burn-in or during its useful life;

all surfaces of the first circuit layer and the second circuit layer with circuitry thereon are internal to the stacked integrated circuit whereby the stacked integrated circuit is its own packaging;

the stacked integrated circuit comprises a plurality of circuit layers wherein two or more circuit layers have similar functioning circuitry in a vertical overlapping position;

the circuitry on the first circuit layer and the second circuit layer is reconfigurable by the use of vertical interconnections between the first circuit layer and the second circuit layer;

the stacked integrated circuit comprises one or more vertical interconnections between the first circuit layer and the second circuit layer having cross-sectional areas that are at least two times larger than any horizontal signal interconnection;

some of the first circuit layer and the second circuit layer are not designed specifically for the particular stacked integrated circuit;

an application-specific function of the stacked integrated circuit is derived from the choice and quantity of circuit layers from previously fabricated, non-application-specific circuit layers;

or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are free-standing;

or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are without the mechanical support of a dielectric;

interconnections of circuitry on at least one of the first circuit layer and the second circuit layer are changed by interconnections on the backside of the circuit layer;

one or snore transistor gates of at least one circuit layer is back biased by forming a contact on the backside of the at least one circuit layer opposite the one or more transistor gates;

I/O drivers for the stacked integrated circuit are physically on a separate circuit layer or on the backside of one of the first circuit layer and the second circuit layer;

in one of the first circuit layer and the second circuit layer dielectric has been predominately removed leaving free-standing metal horizontal and vertical interconnections;

the first circuit layer and the second circuit layer contains a predominately free-standing RF antenna;

one of the first circuit layer and the second circuit layer comprises a MEMS device;

one optical circuit layer couples signals into an electronic circuit layer;

one of the first circuit layer and the second circuit layer comprises a generically programmable automatic testing circuit layer for testing one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers with redundant circuits wherein an interconnection wire length between redundant circuits is approximately equal to or less than a thickness of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers including wireless circuitry for creating multiple data transmission paths between a plurality of stacked ICs, and means for changing one or more wireless data transmission paths between any two stacked ICs as needed;

the stacked integrated circuit comprises a plurality of circuit layers including a plurality of wireless circuits wherein the wireless circuits are used to create a plurality of data transmission paths;

the stacked integrated circuit comprises circuitry for performing full-wafer test and burn-in;

the stacked integrated circuit comprises memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling reconfiguration of the memory circuit layers of the stacked integrated circuit;

the stacked integrated circuit comprises memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling the use of a variable amount of the memory of the stacked integrated circuit;

the stacked integrated circuit comprises a credit-card-shaped enclosure enclosing the stacked integrated circuit;

the stacked integrated circuit comprises a sensing device with sensor devices separated and overlying processing electronics of the sensor devices;

the stacked integrated circuit comprises a stacked programmable logic device having a plurality of circuit layers wherein there is at least one each of a programmable gate circuit layer, a routing circuit layer and a memory circuit layer;

the stacked integrated circuit comprises a stacked programmable logic device having a plurality of circuit layers wherein there is at least one circuit layer comprising automatic test electronics;

the stacked integrated circuit comprises a plurality of circuit layers with processors thereon wherein a non-blocking cross bar interconnects the processors and is integrated onto the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers wherein one or more of the first circuit layer and the second circuit layer comprises analog circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the analog circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers wherein one or more of the first circuit layer and the second circuit layer comprises passive circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the passive circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the at least one integrated circuit comprises a single crystal semiconductor substrate, and wherein said one interconnection passes through and is insulated from said single crystal semiconductor substrate;

the stacked integrated circuit comprises a plurality of interconnections passing through the at least one integrated circuit, wherein at least one of the plurality of interconnections is a redundant interconnection.

57. A stacked integrated circuit comprising:

a first circuit layer; and

a second circuit layer overlying the first circuit layer,

wherein at least one of the first and second circuit layers comprises at least one integrated circuit; and

at least one interconnection between the first circuit layer and the second circuit layer, passing vertically through the at least one integrated circuit;

wherein at least one of the first and second circuit layers is fabricated according to a completed physical circuit design selected from a design library of a plurality of interoperable completed physical circuit layer designs.

58. The stacked integrated circuit of claim 57, wherein the first circuit layer and the second circuit layer each comprise at least one of the following:

a microprocessor, PLD or FPGA circuitry, a passive device array, a DSP, a SERDES, I/O circuitry, memory, and a graphics processor.

59. The stacked integrated circuit of claim 57, wherein the first and second circuit layers each comprise logic circuitry, and wherein at least partial logic circuit redundancy exists between the first and second circuit layers.

60. The stacked integrated circuit of claim 57, comprising at least a third circuit layer, each of the first, second and third circuit layers being either a memory layer or a PLD or FPGA circuit layer.

61. The stacked integrated circuit of claim 60, comprising at least a fourth circuit layer, wherein the circuit layers include a plurality of memory layers and a plurality of PLD or FPGA circuit layers.

62. The stacked integrated circuit of claim 57, wherein the stacked integrated circuit is provided with wireless interconnection capability.

63. The stacked integrated circuit of claim 57, comprising one or more additional circuit layers, wherein all of the circuit layers are bonded together such that no circuitry of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit.

64. The stacked integrated circuit of claim 57, wherein at least one of the first circuit layer and second circuit layer comprises electronic circuitry.

65. The stacked integrated circuit of claim 57, wherein at least one of the first circuit layer and the second circuit layer comprises optical circuitry.

66. The stacked integrated circuit of claim 57, wherein at east one of the first circuit layer and the second circuit layer comprises a MEMS device.

67. The stacked integrated circuit of claim 57, comprising integrated circuit devices fabricated on a backside of one or more of the first and second circuit layers.

68. The stacked integrated circuit of claim 67, wherein the integrated circuit devices comprise at least one of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

69. The stacked integrated circuit of claim 67, wherein he integrated circuit devices comprise at least two of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

70. The stacked integrated circuit of claim 67, wherein the integrated circuit devices comprise all of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

71. The stacked integrated circuit of claim 57, wherein the stacked integrated circuit comprises at least two of the following types of circuit layers:

electronic, optical and MEMS circuit layers.

72. The stacked integrated circuit of claim 57, wherein a dielectric layer is deposited on a backside of one or more of the first circuit layer and the second circuit layer to enhance electrical isolation of an underlying semiconductor device layer.

73. The stacked integrated circuit of claim 57, wherein integrated circuit device fabrication is performed on a backside of one or more of the first and second circuit layers to complete fabrication of integrated circuit devices partially formed on a front side of the one or more of the first and second circuit layers.

74. The stacked integrated circuit of claim 57, wherein integrated circuit fabrication is performed on a backside of one or more of the first circuit layer and the second circuit layer to fabricate one or more memory layers.

75. The stacked integrated circuit of claim 74, wherein the one or more memory layers comprise at least one of MRAM, PRAM, ferroelectric and dendritic memory.

76. The stacked integrated circuit of claim 57, wherein the first circuit layer and the second circuit layer are bonded using a bonding layer made from two or more metal films, one of which has a lower melting point and which will diffuse with an immediately adjacent film.

77. The stacked integrated circuit of claim 76, wherein the bonding layer forms a diffused metal film having a higher melting point than the lower melting point metal film.

78. The stacked integrated circuit of claim 57, wherein at least one of the first circuit layer and the second circuit layer comprises a programmable tester for testing of the stacked integrated circuit during burn-in or during its useful life.

79. The stacked integrated circuit of claim 57, wherein the first and second circuit layers comprise surfaces at least some of which have circuitry formed thereon, wherein all surfaces of the first circuit layer and the second circuit layer with circuitry thereon are internal to the stacked integrated circuit whereby the stacked integrated circuit is its own packaging.

80. The stacked integrated circuit of claim 79, comprising a bonding layer for bonding together the first circuit layer and the second circuit layer, wherein the bonding layer forms a hermetic seal.

81. The stacked integrated circuit of claim 57, comprising a plurality of further circuit layers wherein two or more circuit layers have similar functioning circuitry in a vertical overlapping position.

82. The stacked integrated circuit of claim 57, comprising circuitry on the first circuit layer and the second circuit layer, wherein the circuitry on the first circuit layer and the second circuit layer is reconfigurable by the use of vertical interconnections between the first circuit layer and the second circuit layer.

83. The stacked integrated circuit of claim 57, comprising one or more vertical interconnections between the first circuit layer and the second circuit layer having cross-sectional areas that are at least two times larger than any horizontal signal interconnection on either the first circuit layer or the second circuit layer.

84. The stacked integrated circuit of claim 57, wherein some of the first circuit layer and the second circuit layer are not designed specifically for the stacked integrated circuit.

85. The stacked integrated circuit of claim 57, wherein the stacked integrated circuit performs an application-specific function that is derived from a choice and quantity of circuit layers from among previously fabricated, non-application-specific circuit layers.

86. The stacked integrated circuit of claim 57, wherein one or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are free-standing.

87. The stacked integrated circuit of claim 57, wherein one or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are without the mechanical support of a dielectric layer.

88. The stacked integrated circuit of claim 57, comprising circuitry on at least one of the first circuit layer and the second circuit layer, and interconnections on a backside of the at least one of the first circuit layer and the second circuit layer, wherein interconnections of circuitry on at least one of the first circuit layer and the second circuit layer are changed by interconnections on the backside of the at least one of the first circuit layer and the second circuit layer.

89. The stacked integrated circuit of claim 57, wherein at least one of the first circuit layer and the second circuit layer comprises one or more transistor gates that are biased by forming a contact on a backside of the at least one of the first circuit layer and the second circuit layer opposite the one or more transistor gates.

90. The stacked integrated circuit of claim 57, comprising I/O drivers for the stacked integrated circuit, wherein the I/O drivers are physically stored on a separate circuit layer or on a backside of one of the first circuit layer and the second circuit layer.

91. The stacked integrated circuit of claim 57, wherein at least one of the first circuit layer and the second circuit layer comprises a dielectric layer that has been predominately removed, leaving free-standing metal horizontal and vertical interconnections.

92. The stacked integrated circuit of claim 57, wherein one of the first circuit layer and the second circuit layer comprises a predominately free-standing RE antenna.

93. The stacked integrated circuit of claim 57, wherein at least one of the first circuit layer and the second circuit layer comprises a MEMS device.

94. The stacked integrated circuit of claim 93, wherein the first circuit layer comprises a MEMS device.

95. The stacked integrated circuit of claim 93, comprising another circuit layer, wherein the MEMS device is fabricated as part of the at least one of the first circuit layer and the second circuit layer after bonding of the at least one of the first circuit layer and the second circuit layer to said another circuit layer.

96. The stacked integrated circuit of claim 57, wherein the first and second circuit layers together comprise an optical circuit layer couples signals into an electronic circuit layer.

97. The stacked integrated circuit of claim 57, wherein one of the first circuit layer and the second circuit layer comprises a generically programmable automatic testing circuit layer for testing another one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit.

98. The stacked integrated circuit of claim 57, wherein the first circuit layer and the second circuit layer comprise redundant circuits interconnected by an interconnection wire, wherein an interconnection wire length between the redundant circuits is approximately equal to or less than a thickness of the stacked integrated circuit.

99. The stacked integrated circuit of claim 57, comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein the plurality of circuit layers comprise:

wireless circuitry for creating multiple data transmission paths between a plurality of stacked ICs, and

means for changing one or ore wireless data transmission paths between any two stacked ICs as needed.

100. The stacked integrated circuit of claim 57, comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein the plurality of circuit layers comprise a plurality of wireless circuits configured to create a plurality of data transmission paths.

101. The stacked integrated circuit of claim 57, wherein at least one of the first circuit layer and the second circuit layer comprises circuitry for performing full-wafer test and burn-in.

102. The stacked integrated circuit of claim 57, comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein the plurality of circuit layers together comprise memory control logic and memory circuit layers, and wherein at least one of the plurality of circuit layers comprises memory control logic circuitry enabling reconfiguration of the memory circuit layers of the stacked integrated circuit.

103. The stacked integrated circuit of claim 57, comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein the plurality of circuit layers together comprise memory control logic and memory circuit layers, and wherein at least one of the plurality of circuit layers comprises memory control logic circuitry enabling the use of a variable amount of a memory capacity of the stacked integrated circuit.

104. The stacked integrated circuit of claim 57, comprising a credit-card-shaped enclosure enclosing the stacked integrated circuit.

105. The stacked integrated circuit of claim 57, comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein the plurality of circuit layers together comprise a plurality of sensor devices and processing electronics coupled to the sensor devices, wherein the sensor devices are separated from and overlie the processing electronics coupled to the sensor devices.

106. The stacked integrated circuit of claim 57 wherein the stacked integrated circuit is, a stacked programmable logic device comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein is the plurality of circuit layers comprise at least one each of a programmable gate circuit layer, a routing circuit layer and a memory circuit layer.

107. The stacked integrated circuit of claim 57 wherein the stacked integrated circuit is a stacked programmable logic device comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein at least one circuit layer of the plurality of circuit layers comprising automatic test electronics.

108. The stacked integrated circuit of claim 57, comprising a plurality of circuit layers including the first circuit layer and the second circuit layer, wherein the plurality of circuit layers together comprise a plurality of processors, further comprising a non-blocking cross bar configured to interconnect the plurality of processors, wherein the non-blocking cross bar is integrated onto one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit.

109. The stacked integrated circuit of claim 57, wherein one or more of the first circuit layer and the second circuit layer comprises analog circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the analog circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit.

110. The stacked integrated circuit of claim 57, wherein one or more of the first circuit layer and the second circuit layer comprises passive circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the passive circuitry elements to circuitry on one or more of the circuit layers of the stacked integrated circuit.

111. The stacked integrated circuit of claim 57, wherein the at least one integrated circuit comprises a single crystal semiconductor substrate, and wherein said one interconnection passes through and is insulated from said single crystal semiconductor substrate.

112. The stacked integrated circuit of claim 57, comprising a plurality of interconnections passing through the at least one integrated circuit, wherein at least one of the plurality of interconnections is a redundant interconnection.

113. The stacked integrated circuit of claim 57, wherein at least two of the following:

the first circuit layer and the second circuit layer each comprise at least one of a microprocessor, PLD or FPGA circuitry, a passive device array, a DSP, a SERDES, I/O circuitry, memory, and a graphics processor;

the stacked integrated circuit comprises at least partial logic circuit redundancy between different layers;

the stacked integrated circuit comprises at least three layers, each of the three layers being either a memory layer or a PLD or FPGA circuit layer;

the stacked integrated circuit is provided with wireless interconnection capability;

the stacked integrated circuit comprises a plurality of circuit layers bonded together such that no circuitry of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit;

at least one of the first circuit layer and second circuit layer comprises electronic circuitry;

at least one of the first circuit layer and second circuit layer comprises optical circuitry;

at least one of the first circuit layer and second circuit layer comprises a MEMS device;

the stacked integrated circuit comprises integrated circuit devices fabricated on the backside of one or more circuit layers;

the stacked integrated circuit comprises a plurality of circuit layers including at least two of a group consisting of electronic, optical and MEMS circuit layers;

the stacked integrated circuit comprises integrated circuit devices fabricated on the backside of one or more circuit layers;

a dielectric layer is deposited on the backside of one or more of the first circuit layer and the second circuit layer to enhance electrical isolation of an underlying semiconductor device layer;

integrated circuit device fabrication is performed on the backside of one or more circuit layers to complete the fabrication of integrated circuit devices partially formed on the front side of the one or more circuit layers;

integrated circuit fabrication is performed on the backside of one or more of the first circuit layer and the second circuit layer to fabricate one or more memory layers;

the first circuit layer and the second circuit layer are bonded using bonding layers made from two or more metal films, one of which has a lower melting point and which will diffuse with an immediately adjacent film;

at least one of the first circuit layer and the second circuit layer comprises a programmable tester for testing of the stacked integrated circuit during burn-in or during its useful life;

all surfaces of the first circuit layer and the second circuit layer with circuitry thereon are internal to the stacked integrated circuit whereby the stacked integrated circuit is its own packaging;

the stacked integrated circuit comprises a plurality of circuit layers wherein two or more circuit layers have similar functioning circuitry in a vertical overlapping position;

circuitry is formed on the first circuit layer and the second circuit layer, the circuitry on the first circuit layer and the second circuit layer being reconfigurable by the use of vertical interconnections between the first circuit layer and the second circuit layer;

the stacked integrated circuit comprises one or more vertical interconnections between the first circuit layer and the second circuit layer having cross-sectional areas that are at least two times larger than any horizontal signal interconnection;

some of the first circuit layer and the second circuit layer are not designed specifically for the particular stacked integrated circuit;

an application-specific function of the stacked integrated circuit is derived from the choice and quantity of circuit layers from previously fabricated, non-application-specific circuit layers;

or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are free-standing;

or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are without the mechanical support of a dielectric;

interconnections of circuitry on at least one of the first circuit layer and the second circuit layer are changed by interconnections on the backside of the circuit layer;

one or more transistor gates of at least one circuit layer is back biased by forming a contact on the backside of the at least one circuit layer opposite the one or more transistor gates;

I/O drivers for the stacked integrated circuit are physically on a separate circuit layer or on the backside of one of the first circuit layer and the second circuit layer;

in one of the first circuit layer and the second circuit layer dielectric has been predominately removed leaving free-standing metal horizontal and vertical interconnections;

the first circuit layer and the second circuit layer contains a predominately free-standing RF antenna;

one of the first circuit layer and the second circuit layer comprises a MEMS device;

one optical circuit layer couples signals into an electronic circuit layer;

one of the first circuit layer and the second circuit layer comprises a generically programmable automatic testing circuit layer for testing one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers with redundant circuits wherein an interconnection wire length between redundant circuits is approximately equal to or less than a thickness of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers including wireless circuitry for creating multiple data transmission paths between a plurality of stacked ICs, and means for changing one or more wireless data transmission paths between any two stacked ICs as needed;

the stacked integrated circuit comprises a plurality of circuit layers including a plurality of wireless circuits wherein the wireless circuits are used to create a plurality of data transmission paths;

the stacked integrated circuit comprises circuitry for performing full-wafer test and burn-in;

the stacked integrated circuit comprises memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling reconfiguration of the memory circuit layers of the stacked integrated circuit;

the stacked integrated circuit comprises memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling the use of a variable amount of the memory of the stacked integrated circuit;

the stacked integrated circuit comprises a credit-card-shaped enclosure enclosing the stacked integrated circuit;

the stacked integrated circuit comprises a sensing device with sensor devices separated and overlying processing electronics of the sensor devices;

the stacked integrated circuit comprises a stacked programmable logic device having a plurality of circuit layers wherein there is at least one each of a programmable gate circuit layer, a routing circuit layer and a memory circuit layer;

the stacked integrated circuit comprises a stacked programmable logic device having a plurality of circuit layers wherein there is at least one circuit layer comprising automatic test electronics;

the stacked integrated circuit comprises a plurality of circuit layers with processors thereon wherein a non-blocking cross bar interconnects the processors and is integrated onto the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers wherein one or more of the first circuit layer and the second circuit layer comprises analog circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the analog circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers wherein one or more of the first circuit layer and the second circuit layer comprises passive circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the passive circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the at least one integrated circuit comprises a single crystal semiconductor substrate, and wherein said one interconnection passes through and is insulated from said single crystal semiconductor substrate;

the stacked integrated circuit comprises a plurality of interconnections passing through the at least one integrated circuit, wherein at least one of the plurality of interconnections is a redundant interconnection.

114. The stacked integrated circuit of claim 57, wherein at least three of the following:

the first circuit layer and the second circuit layer each comprise at least one of a microprocessor, PLD or FPGA circuitry, a passive device array, a DSP, a SERDES, I/O circuitry, memory, and a graphics processor;

the stacked integrated circuit comprises at least partial logic circuit redundancy between different layers;

the stacked integrated circuit comprises at least three layers, each of the three layers being either a memory layer or a PLD or FPGA circuit layer;

the stacked integrated circuit is provided with wireless interconnection capability;

the stacked integrated circuit comprises a plurality of circuit layers bonded together such that no circuitry of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit;

at least one of the first circuit layer and second circuit layer comprises electronic circuitry;

at least one of the first circuit layer and second circuit layer comprises optical circuitry;

at least one of the first circuit layer and second circuit layer comprises a MEMS device;

the stacked integrated circuit comprises integrated circuit devices fabricated on the backside of one or more circuit layers;

the stacked integrated circuit comprises a plurality of circuit layers including at least two of a group consisting of electronic, optical and MEMS circuit layers;

the stacked integrated circuit comprises integrated circuit devices fabricated on the backside of one or more circuit layers;

a dielectric layer is deposited on the backside of one or more of the first circuit layer and the second circuit layer to enhance electrical isolation of an underlying semiconductor device layer;

integrated circuit device fabrication is performed on the backside of one or more circuit layers to complete the fabrication of integrated circuit devices partially formed on the front side of the one or more circuit layers;

integrated circuit fabrication is performed on the backside of one or more of the first circuit layer and the second circuit layer to fabricate one or more memory layers;

the first circuit layer and the second circuit layer are bonded using bonding layers made from two or more metal films, one of which has a lower melting point and which will diffuse with an immediately adjacent film;

at least one of the first circuit layer and the second circuit layer comprises a programmable tester for testing of the stacked integrated circuit during bum-in or during its useful life;

all surfaces of the first circuit layer and the second circuit layer with circuitry thereon are internal to the stacked integrated circuit whereby the stacked integrated circuit is its own packaging;

the stacked integrated circuit comprises a plurality of circuit layers wherein two or more circuit layers have similar functioning circuitry in a vertical overlapping position;

circuitry is formed on the first circuit layer and the second circuit layer, the circuitry on the first circuit layer and the second circuit layer being reconfigurable by the use of vertical interconnections between the first circuit layer and the second circuit layer;

the stacked integrated circuit comprises one or more vertical interconnections between the first circuit layer and the second circuit layer having cross-sectional areas that are at least two times larger than any horizontal signal interconnection;

some of the first circuit layer and the second circuit layer are not designed specifically for the particular stacked integrated circuit;

an application-specific function of the stacked integrated circuit is derived from the choice and quantity of circuit layers from previously fabricated, non-application-specific circuit layers;

or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are free-standing;

or more of the first circuit layer and the second circuit layer have portions of horizontal interconnections that are without the mechanical support of a dielectric;

interconnections of circuitry on at least one of the first circuit layer and the second circuit layer are changed by interconnections on the backside of the circuit layer;

one or more transistor gates of at least one circuit layer is back biased by forming a contact on the backside of the at least one circuit layer opposite the one or more transistor gates;

I/O drivers for the stacked integrated circuit are physically on a separate circuit layer or on the backside of one of the first circuit layer and the second circuit layer;

in one of the first circuit layer and the second circuit layer dielectric has been predominately removed leaving free-standing metal horizontal and vertical interconnections;

the first circuit layer and the second circuit layer contains a predominately free-standing RF antenna;

one of the first circuit layer and the second circuit layer comprises a MEMS device;

one optical circuit layer couples signals into an electronic circuit layer;

one of the first circuit layer and the second circuit layer comprises a generically programmable automatic testing circuit layer for testing one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers with redundant circuits wherein an interconnection wire length between redundant circuits is approximately equal to or less than a thickness of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers including wireless circuitry for creating multiple data transmission paths between a plurality of stacked ICs, and means for changing one or more wireless data transmission paths between any two stacked ICs as needed;

the stacked integrated circuit comprises a plurality of circuit layers including a plurality of wireless circuits wherein the wireless circuits are used to create a plurality of data transmission paths;

the stacked integrated circuit comprises circuitry for performing full-wafer test and burn-in;

the stacked integrated circuit comprises memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling reconfiguration of the memory circuit layers of the stacked integrated circuit;

the stacked integrated circuit comprises memory control logic and memory circuit layers wherein at least one circuit layer has memory control logic circuitry enabling the use of a variable amount of the memory of the stacked integrated circuit;

the stacked integrated circuit comprises a credit-card-shaped enclosure enclosing the stacked integrated circuit;

the stacked integrated circuit comprises a sensing device with sensor devices separated and overlying processing electronics of the sensor devices;

the stacked integrated circuit comprises a stacked programmable logic device having a plurality of circuit layers wherein there is at least one each of a programmable gate circuit layer, a routing circuit layer and a memory circuit layer;

the stacked integrated circuit comprises a stacked. programmable logic device having a plurality of circuit layers wherein there is at least one circuit layer comprising automatic test electronics;

the stacked integrated circuit comprises a plurality of circuit layers with processors thereon wherein a non-blocking cross bar interconnects the processors and is integrated onto the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers wherein one or more of the first circuit layer and the second circuit layer comprises analog circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the analog circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the stacked integrated circuit comprises a plurality of circuit layers wherein one or more of the first circuit layer and the second circuit layer comprises passive circuitry elements and one or more of the first circuit layer and the second circuit layer comprises reconfigurable circuitry which can be programmed to interconnect the passive circuitry elements to circuitry on one or more of the first circuit layer and the second circuit layer of the stacked integrated circuit;

the at least one integrated circuit comprises a single crystal semiconductor substrate, and wherein said one interconnection passes through and is insulated from said single crystal semiconductor substrate;

the stacked integrated circuit comprises a plurality of interconnections passing through the at least one integrated circuit, wherein at least one of the plurality of interconnections is a redundant interconnection.