Wide band and radio frequency waveguide and hybrid integration in a silicon package

• US 8,587,106 B2
• Filed: 06/11/2007
• Issued: 11/19/2013
• Est. Priority Date: 06/09/2006
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Bozler, Carl O., Muldavin, Jeremy, Wyatt, Peter W., Keast, Craig L., Rabe, Steven
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US11/761,108
• Publication Number:
  US 20100019872A1
• Time in Patent Office: 2,353 Days
• Field of Search: 257678-680, 257/700, 257/730, 257/750, 257/758, 257/E23.001, 333/248, 361/752
• US Class Current: 257/680
• CPC Class Codes: B81B 2201/014 having a cantilever fixed on one side connected to one or more dimples
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/0064 for protecting against electromagnetic or electrostatic interferences
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01P 3/08 Microstrips; Strip lines

Abstract

A device includes a device wafer having a circuit component formed thereon and having vias formed therein and a cap wafer bonded to the device wafer. The cap wafer has a cavity therein. The cavity has a post formed therein, and the post is positioned to mechanically support the vias formed in the device wafer. The cavity has a volume, the volume substantially enclosing the circuit component formed on the device wafer. The cavity has a width and height such that an impedance of a transmission line is dependent upon the width and height of the cavity, or the impedance of a transmission line is dependent upon the width of a center conductor within the cavity.

Claims

1. A device, comprising:

a device wafer having a circuit component formed thereon; and

a cap wafer bonded to said device wafer;

said cap wafer having a cavity therein, said cavity having a width and height such that an impedance of a transmission line is dependent upon said width and height of said cavity;

said cavity having a volume, the volume substantially enclosing said circuit component formed on said device wafer;

said cap wafer being hermetically sealed to said device wafer.

2. The device as claimed in claim 1, wherein said width and height of said cavity create a transmission line having an impedance of 50 ohm.

3. The device as claimed in claim 1, wherein said width and height of said cavity create a transmission line having an impedance of 20 ohm.

4. The device as claimed in claim 1, wherein said width and height of said cavity create a transmission line having an impedance of 75 ohm.

5. The device as claimed in claim 1, wherein said cavity has a width between 50 microns and 1000 microns.

6. The device as claimed in claim 1, wherein said cavity has a height between 10 microns and 200 microns.

7. The device as claimed in claim 5, wherein said cavity has a height between 10 microns and 200 microns.

8. The device as claimed in claim 1, wherein said device wafer is silicon-on-insulator.

9. The device as claimed in claim 1, wherein said wafer cap is silicon.

10. The device as claimed in claim 1, wherein said cavity has a metal layer formed on a surface thereof.

11. The device as claimed in claim 1, wherein said cavity has a layer of gold formed on a surface thereof.

12. The device as claimed in claim 1, wherein said cap wafer is bonded to said device wafer using thermo-compression.

13. The device as claimed in claim 1, wherein said cap wafer is bonded to said device wafer using gold.

14. A device, comprising:

a device wafer having a center conductor formed thereon; and

a cap wafer bonded to said device wafer;

said cap wafer having a cavity therein, said cavity having a width and height;

said center conductor having a width such that an impedance of said center conductor within said cavity is dependent upon said width of said center conductor;

said cap wafer being hermetically sealed to said device wafer.

15. The device as claimed in claim 14, wherein said width of said center conductor creates a transmission line having an impedance of 50 ohm.

16. The device as claimed in claim 14, wherein said width of said center conductor creates a transmission line having an impedance of 20 ohm.

17. The device as claimed in claim 14, wherein said width of said center conductor creates a transmission line having an impedance of 75 ohm.

18. The device as claimed in claim 14, wherein said width of said center conductor has a width between 10 microns and substantially a width of said cavity.

19. The device as claimed in claim 14, wherein said impedance of the transmission line is dependent upon said width of said center conductor and said width of said cavity.

20. The device as claimed in claim 19, wherein said cavity has a width between 50 microns and 1000 microns.

21. The device as claimed in claim 14, wherein said cavity has a width between 50 microns and 1000 microns.

22. The device as claimed in claim 14, wherein said cavity has a height between 10 microns and 200 microns.

23. The device as claimed in claim 21, wherein said cavity has a height between 10 microns and 200 microns.

24. The device as claimed in claim 14, wherein said device wafer is silicon-on-insulator.

25. The device as claimed in claim 14, wherein said wafer cap is silicon.

26. The device as claimed in claim 14, wherein said cavity has a metal layer formed on a surface thereof.

27. The device as claimed in claim 14, wherein said cavity has a layer of gold formed on a surface thereof.

28. The device as claimed in claim 14, wherein said cap wafer is bonded to said device wafer using thermo-compression.

29. The device as claimed in claim 14, wherein said cap wafer is bonded to said device wafer using gold.

30. A device, comprising:

a device wafer having a circuit component formed thereon and having vias formed therein; and

a cap wafer bonded to said device wafer;

said cap wafer having a cavity therein, said cavity having a post formed therein;

said post being positioned to mechanically support said vias formed in said device wafer;

said cavity having a volume, the volume substantially enclosing said circuit component formed on said device wafer;

said cap wafer being hermetically sealed to said device wafer.

31. The device as claimed in claim 30, wherein said device wafer is silicon-on-insulator.

32. The device as claimed in claim 30, wherein said wafer cap is silicon.

33. The device as claimed in claim 30, wherein said cavity has a metal layer formed on a surface thereof.

34. The device as claimed in claim 30, wherein said cavity has a layer of gold formed on a surface thereof.

35. The device as claimed in claim 30, wherein said post is silicon.

36. The device as claimed in claim 30, wherein said cap wafer is bonded to said device wafer using thermo-compression.

37. The device as claimed in claim 30, wherein said cap wafer is bonded to said device wafer using gold.

38. A MEMS switch, comprising:

a device wafer having a MEMS component formed thereon and having vias formed therein;

a cap wafer bonded to said device wafer; and

a conductor bonded to said vias;

said cap wafer having a cavity therein, said cavity having a post formed therein;

said post being positioned to mechanically support said vias formed in said device wafer;

said cavity having a volume, the volume substantially enclosing said MEMS component formed on said device wafer;

said cap wafer being hermetically sealed to said device wafer.

39. The MEMS switch as claimed in claim 38, further comprises a moisture sensor.

40. The MEMS switch as claimed in claim 38, wherein said device wafer is silicon-on-insulator.

41. The MEMS switch as claimed in claim 38, wherein said wafer cap is silicon.

42. The MEMS switch as claimed in claim 38, wherein said cavity has a metal layer formed on a surface thereof.

43. The MEMS switch as claimed in claim 38, wherein said cavity has a layer of gold formed on a surface thereof.

44. The MEMS switch as claimed in claim 38, wherein said post is silicon.

45. The MEMS switch as claimed in claim 38, wherein said cap wafer is bonded to said device wafer using thermo-compression.

46. The MEMS switch as claimed in claim 38, wherein said cap wafer is bonded to said device wafer using gold.

47. The MEMS switch as claimed in claim 38, wherein said vias are bump bonded to said conductor.

48. A device, comprising:

a device wafer having a circuit component formed thereon;

a first cap wafer bonded to a first side of said device wafer; and

a second cap wafer bonded to a second side of said device wafer;

said first cap wafer having a first cap wafer cavity therein, said first cap wafer cavity having a width and height such that an impedance of a transmission line is dependent upon said width and height of said first cap wafer cavity;

said second cap wafer having a second cap wafer cavity therein;

said first and second cap wafers being hermetically sealed to said device wafer.

49. The device as claimed in claim 48, wherein said width and height of said first cap wafer cavity create a transmission line having an impedance of 50 ohm.

50. The device as claimed in claim 48, wherein said width and height of said first cap wafer cavity create a transmission line having an impedance of 20 ohm.

51. The device as claimed in claim 48, wherein said width and height of said first cap wafer cavity create a transmission line having an impedance of 75 ohm.

52. The device as claimed in claim 48, wherein said first cap wafer cavity has a width between 50 microns and 1000 microns.

53. The device as claimed in claim 48, wherein said first cap wafer cavity has a height between 10 microns and 200 microns.

54. The device as claimed in claim 52, wherein said first cap wafer cavity has a height between 10 microns and 200 microns.

55. The device as claimed in claim 48, wherein said second cap wafer cavity includes a heat sink formed therein.

56. The device as claimed in claim 48, wherein said second cap wafer cavity provides micro-channel cooling.

57. A device, comprising:

a device wafer having a center conductor formed thereon;

a first cap wafer bonded to a first side of said device wafer; and

a second cap wafer bonded to a second side of said device wafer;

said first cap wafer having a first cap wafer cavity therein, said first cap wafer cavity having a width and height;

said center conductor having a width such that an impedance of said center conductor is dependent upon said width of said center conductor;

said second cap wafer having a second cap wafer cavity therein;

said first and second cap wafers being hermetically sealed to said device wafer.

58. The device as claimed in claim 57, wherein said width of said center conductor creates a transmission line having an impedance of 50 ohm.

59. The device as claimed in claim 57, wherein said width of said center conductor creates a transmission line having an impedance of 20 ohm.

60. The device as claimed in claim 57, wherein said width of said center conductor creates a transmission line having an impedance of 75 ohm.

61. The device as claimed in claim 57, wherein said width of said center conductor has a width between 10 microns and substantially a width of said cavity.

62. The device as claimed in claim 57, wherein said impedance of the transmission line is dependent upon said width of said center conductor and said width of said cavity.

63. The device as claimed in claim 62, wherein said cavity has a width between 50 microns and 1000 microns.

64. The device as claimed in claim 57, wherein said cavity has a width between 50 microns and 1000 microns.

65. The device as claimed in claim 57, wherein said cavity has a height between 10 microns and 200 microns.

66. The device as claimed in claim 64, wherein said cavity has a height between 10 microns and 200 microns.

67. The device as claimed in claim 57, wherein said second cap wafer cavity includes a heat sink formed therein.

68. The device as claimed in claim 57, wherein said second cap wafer cavity provides micro-channel cooling.

69. A device, comprising:

a device wafer having a circuit component formed thereon and having vias formed therein;

a first cap wafer bonded to a first side of said device wafer; and

a second cap wafer bonded to a second side of said device wafer;

said first cap wafer having a first cap wafer cavity therein, said first cap wafer cavity having a post formed therein;

said second cap wafer having a second cap wafer cavity therein, said second cap wafer cavity having a post formed therein;

said post in said first cap wafer cavity being positioned to mechanically support said vias formed in said device wafer;

said post in said second cap wafer cavity being positioned to mechanically support said vias formed in said device wafer;

said first cap wafer cavity having a volume, the volume substantially enclosing said circuit component formed on said device wafer;

said first and second cap wafers being hermetically sealed to said device wafer.

70. The device as claimed in claim 69, wherein said device wafer is silicon-on-insulator.

71. The device as claimed in claim 69, wherein said first and second cap wafers are silicon.

72. The device as claimed in claim 69, wherein said first and second cap wafer cavities have a metal layer formed on a surface thereof.

73. The device as claimed in claim 69, wherein said first and second cap wafer cavities have a layer of gold formed on a surface thereof.

74. The device as claimed in claim 69, wherein said posts are silicon.

75. The device as claimed in claim 69, wherein said first and second cap wafer are bonded to said device wafer using thermo-compression.

76. The device as claimed in claim 69, wherein said first and second cap wafer are bonded to said device wafer using gold.

77. The device as claimed in claim 69, wherein said second cap wafer cavity includes a heat sink formed therein.

78. The device as claimed in claim 69, wherein said second cap wafer cavity provides micro-channel cooling.