Semiconductor integrated circuit

• US 8,587,342 B2
• Filed: 05/15/2012
• Issued: 11/19/2013
• Est. Priority Date: 05/20/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yakubo, Yuto, Nagatsuka, Shuhei
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US13/471,920
• Publication Number:
  US 20120293207A1
• Time in Patent Office: 553 Days
• Field of Search: 326/102, 326/83, 326/52, 326/55, 326/95, 326/112, 326/113, 326/122, 327/408, 327/409
• US Class Current: 326/102
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon.

Claims

1. A semiconductor integrated circuit including a logic circuit, the logic circuit comprising:

a comparator configured to compare potentials of two output nodes;

a charge holding portion electrically connected to the comparator, the charge holding portion comprising;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor; and

an output-node-potential determining portion,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the seventh transistor and one of the two output nodes,

wherein the other of the source and the drain of the first transistor is electrically connected to the other of the two output nodes,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and drain of the seventh transistor and the output-node-potential determining portion,

wherein the other of the source and the drain of the third transistor is electrically connected to the output-node-potential determining portion,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,

wherein the other of the source and the drain of the second transistor is configured to receive a first signal input,

wherein the other of the source and the drain of the fourth transistor is configured to receive a second signal input,

wherein the other of the source and the drain of the sixth transistor is configured to receive a third signal input, and

wherein the other of the source and the drain of the eighth transistor is configured to receive a fourth signal input.

2. The semiconductor integrated circuit according to claim 1,

wherein the comparator comprises a first p-channel transistor, a second p-channel transistor, a third p-channel transistor, and a fourth p-channel transistor,

wherein each of a gate of the first p-channel transistor and a gate of the second p-channel transistor is supplied with a clock signal,

wherein a gate of the third p-channel transistor is electrically connected to one of the two output nodes, and

wherein a gate of the fourth p-channel transistor is electrically connected to the other of the two output nodes.

3. The semiconductor integrated circuit according to claim 1,

wherein the output-node-potential determining portion is one n-channel transistor,

wherein a gate of the n-channel transistor is supplied with a clock signal, and

wherein one of a source and a drain of the n-channel transistor is electrically connected to a ground potential terminal.

4. The semiconductor integrated circuit according to claim 3, wherein the n-channel transistor comprises an oxide semiconductor layer.

5. The semiconductor integrated circuit according to claim 1,

wherein the comparator comprises a first n-channel transistor, a second n-channel transistor, a third n-channel transistor, and a fourth n-channel transistor,

wherein each of a gate of the first n-channel transistor and a gate of the second n-channel transistor is supplied with a clock signal,

wherein a gate of the third n-channel transistor is electrically connected to a first output node, and

wherein a gate of the fourth n-channel transistor is electrically connected to a second output node.

6. The semiconductor integrated circuit according to claim 5, wherein each of the first n-channel transistor, the second n-channel transistor, the third n-channel transistor and the fourth n-channel transistor comprises an oxide semiconductor.

7. The semiconductor integrated circuit according to claim 1,

wherein the output-node-potential determining portion is one p-channel transistor,

wherein a gate of the p-channel transistor is supplied with a clock signal, and

wherein one of a source and a drain of the p-channel transistor is electrically connected to a power supply potential terminal.

8. The semiconductor integrated circuit according to claim 1, wherein the charge holding portion further comprises:

a first storage capacitor electrically connected to the gate of the first transistor and one of the source and the drain of the second transistor;

a second storage capacitor electrically connected to the gate of the third transistor and one of the source and the drain of the fourth transistor;

a third storage capacitor electrically connected to the gate of the fifth transistor and one of the source and the drain of the sixth transistor; and

a fourth storage capacitor electrically connected to the gate of the seventh transistor and one of the source and the drain of the eighth transistor.

9. The semiconductor integrated circuit according to claim 1,

wherein the first transistor and the second transistor are stacked with each other,

wherein the third transistor and the fourth transistor are stacked with each other,

wherein the fifth transistor and the sixth transistor are stacked with each other, and

wherein the seventh transistor and the eighth transistor are stacked with each other.

10. The semiconductor integrated circuit according to claim 1,

wherein the first transistor comprises a first layer comprising silicon,

wherein the second transistor comprises a second layer comprising an oxide semiconductor,

wherein the third transistor comprises a third layer comprising silicon,

wherein the fourth transistor comprises a fourth layer comprising an oxide semiconductor,

wherein the fifth transistor comprises a fifth layer comprising silicon,

wherein the sixth transistor comprises a sixth layer comprising an oxide semiconductor,

wherein the seventh transistor comprises a seventh layer comprising silicon, and

wherein the eighth transistor comprises an eighth layer comprising an oxide semiconductor.

11. A semiconductor device including a logic circuit, the logic circuit comprising:

a comparator configured to compare potentials of a first output node and a second output node;

a charge holding portion electrically connected to the comparator, the charge holding portion comprising;

a first circuit comprising a first terminal and a second terminal, the first circuit comprising a first transistor and a second transistor; and

a second circuit comprising a third terminal and a fourth terminal, the second circuit comprising a third transistor and a fourth transistor; and

an output-node-potential determining portion,

wherein the first transistor and the second transistor are electrically connected in series,

wherein the third transistor and the fourth transistor are electrically connected in parallel,

wherein the first terminal is electrically connected to the first output node,

wherein the third terminal is electrically connected to the second output node,

wherein the second terminal and the fourth terminal are electrically connected to the output-node-potential determining portion,

wherein a gate of the first transistor is configured to receive and hold a first signal input,

wherein a gate of the second transistor is configured to receive and hold a second signal input,

wherein a gate of the third transistor is configured to receive and hold a third signal input, and

wherein a gate of the fourth transistor is configured to receive and hold a fourth signal input.

12. The semiconductor device according to claim 11,

wherein the comparator comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,

wherein the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are one of n-channel type and p-channel type,

wherein each of a gate of the fifth transistor and a gate of the sixth transistor is supplied with a clock signal,

wherein a gate of the seventh transistor is electrically connected to the first output node, and

wherein a gate of the eighth transistor is electrically connected to the second output node.

13. The semiconductor device according to claim 12,

wherein the output-node-potential determining portion is a ninth transistor,

wherein the ninth transistor is n-channel type when the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are p-channel type and the ninth transistor is p-channel type when the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are n-channel type,

wherein a gate of the ninth transistor is supplied with the clock signal, and

wherein one of a source and a drain of the ninth transistor is electrically connected to a ground potential terminal when the ninth transistor is n-channel type and to a power supply potential terminal when the ninth transistor is p-channel type.

14. The semiconductor device according to claim 11, wherein a gate of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is connected to one of a source and a drain of a transistor.

15. The semiconductor device according to claim 14, wherein the transistor comprises an oxide semiconductor layer.

16. The semiconductor device according to claim 11, wherein the charge holding portion further comprises:

a first storage capacitor electrically connected to the gate of the first transistor;

a second storage capacitor electrically connected to the gate of the second transistor;

a third storage capacitor electrically connected to the gate of the third transistor; and

a fourth storage capacitor electrically connected to the gate of the fourth transistor.