Power efficient multiplexer
First Claim
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1. A circuit comprising:
- means for outputting at least one bit and a complement of the at least one bit;
means for selectively passing one of a plurality of input signals by using the at least one bit and the complement outputted by the means for outputting; and
means for inverting the one of the plurality of input signals passed by the means for selectively passing, wherein the means for inverting is operable independently of the at least one bit and the complement and a state of a clock signal.
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Abstract
A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.
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Citations
13 Claims
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1. A circuit comprising:
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means for outputting at least one bit and a complement of the at least one bit; means for selectively passing one of a plurality of input signals by using the at least one bit and the complement outputted by the means for outputting; and means for inverting the one of the plurality of input signals passed by the means for selectively passing, wherein the means for inverting is operable independently of the at least one bit and the complement and a state of a clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit comprising:
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means for outputting at least one bit and a complement of the at least one bit; means for inverting operable to invert independently of the at least one bit and the complement and a state of a clock signal; first means for passing a first input signal to the means for inverting; and second means for passing a second input signal to the means for inverting, wherein the first means for passing and the second means for passing are operable to pass one of the first input signal and the second input signal by using the at least one bit and the complement outputted by the means for outputting. - View Dependent Claims (10, 11, 12, 13)
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Specification