AC supply noise reduction in a 3D stack with voltage sensing and clock shifting
First Claim
1. An alternating current supply noise reducer for a 3D chip stack having two or more strata, each of the two or more strata having a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon, the alternating current supply noise reducer comprising:
- a plurality of voltage droop sensors for detecting alternating current supply noise in the plurality of power distribution circuits, one or more of the plurality of voltage droop sensors being respectively arranged on at least some of the two or more strata; and
a plurality of skew adjusters for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise, each of the plurality of skew adjusters being respectively arranged on the at least some of the two or more strata.
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Accused Products
Abstract
There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.
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Citations
25 Claims
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1. An alternating current supply noise reducer for a 3D chip stack having two or more strata, each of the two or more strata having a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon, the alternating current supply noise reducer comprising:
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a plurality of voltage droop sensors for detecting alternating current supply noise in the plurality of power distribution circuits, one or more of the plurality of voltage droop sensors being respectively arranged on at least some of the two or more strata; and a plurality of skew adjusters for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise, each of the plurality of skew adjusters being respectively arranged on the at least some of the two or more strata. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for reducing alternating current supply noise in a 3D chip stack having two or more strata, each of the two or more strata having a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon, the method comprising:
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respectively arranging one or more of a plurality of voltage droop sensors on at least some of the two or more strata to detect alternating current supply noise in the plurality of power distribution circuits; and respectively arranging each of a plurality of skew adjusters on the at least some of the two or more strata to delay one or more clock signals provided by the plurality of clock distribution networks responsive to an amount of the alternating current supply noise. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A 3D chip stack having two or more strata, the chip stack comprising:
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a plurality of power distribution circuits, each being arranged on a respective one of the two or more strata for providing power signals to various locations thereon; a plurality of clock distribution circuits, each being arranged on the respective one of the two or more strata for providing clock signals to particular locations thereon; a plurality of voltage droop sensors, one or more being respectively arranged on at least some of the two or more strata for detecting alternating current supply noise in the power signals; and a plurality of skew adjusters, each being respectively arranged on the at least some of the two or more strata for delaying one or more of the clock signals responsive to an amount of the alternating current supply noise. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method for providing a 3D chip stack having two or more strata with reduced alternating current supply noise, the method comprising:
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arranging each of a plurality of power distribution circuits on a respective one of the two or more strata to provide power signals to various locations thereon; arranging each of a plurality of clock distribution circuits on the respective one of the two or more strata to provide clock signals to particular locations thereon; respectively arranging one or more of a plurality of voltage droop sensors on at least some of the two or more strata to detect alternating current supply noise in the power signals; and respectively arranging each of a plurality of skew adjusters on the at least some of the two or more strata to delay one or more of the clock signals responsive to an amount of the alternating current supply noise.
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Specification