AC supply noise reduction in a 3D stack with voltage sensing and clock shifting

• US 8,587,357 B2
• Filed: 08/25/2011
• Issued: 11/19/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Jae-Joon, Lin, Yu-Shiang, Pang, Liang-Teck, Silberman, Joel A.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US13/217,406
• Publication Number:
  US 20130049828A1
• Time in Patent Office: 817 Days
• Field of Search: 327551-559, 327336-337, 327/34, 327291-195, 327291-296
• US Class Current: 327/296
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices

Abstract

There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.

Claims

1. An alternating current supply noise reducer for a 3D chip stack having two or more strata, each of the two or more strata having a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon, the alternating current supply noise reducer comprising:

a plurality of voltage droop sensors for detecting alternating current supply noise in the plurality of power distribution circuits, one or more of the plurality of voltage droop sensors being respectively arranged on at least some of the two or more strata; and

a plurality of skew adjusters for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise, each of the plurality of skew adjusters being respectively arranged on the at least some of the two or more strata.

2. The alternating current supply noise reducer of claim 1, wherein the amount is represented by an amplitude of the alternating current supply noise.

3. The alternating current supply noise reducer of claim 1, wherein each of the plurality of voltage droop sensors determines an average amount of the alternating current supply noise over a respective one of the two or more strata.

4. The alternating current supply noise reducer of claim 1, wherein a delay provided by the plurality of skew adjusters is adjusted one stratum at a time when the two or more strata comprise at least three strata.

5. The alternating current supply noise reducer of claim 1, wherein a delay provided by at least one of the plurality of skew adjusters on a given one of the two or more strata is adjusted until the amount of the alternating current supply noise on the given one of the two or more strata is below a predetermined threshold.

6. The alternating current supply noise reducer of claim 1, wherein each of the plurality of clock distribution circuits comprises a power grid having a plurality of sectors, and wherein each of the plurality of voltage droop sensors is located within or proximate to a respective one of the plurality of sectors in the at least some of the two or more strata.

7. The alternating current supply noise reducer of claim 1, wherein at least one of the plurality of voltage droop sensors and at least one of the plurality of skew adjusters, both located on a same one of the two or more strata, are used to respectively detect the alternating current supply noise on a different one of the two or more strata and to delay the one or more clock signals on the different one of the two or more strata.

8. A method for reducing alternating current supply noise in a 3D chip stack having two or more strata, each of the two or more strata having a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon, the method comprising:

respectively arranging one or more of a plurality of voltage droop sensors on at least some of the two or more strata to detect alternating current supply noise in the plurality of power distribution circuits; and

respectively arranging each of a plurality of skew adjusters on the at least some of the two or more strata to delay one or more clock signals provided by the plurality of clock distribution networks responsive to an amount of the alternating current supply noise.

9. The method of claim 8, wherein the amount is represented by an amplitude of the alternating current supply noise.

10. The method of claim 8, wherein each of the plurality of voltage droop sensors determines an average amount of the alternating current supply noise over a respective one of the two or more strata.

11. The method of claim 8, further comprising adjusting a delay provided by the plurality of skew adjusters one stratum at a time when the two or more strata comprise at least three strata.

12. The method of claim 8, further comprising adjusting a delay provided by at least one of the plurality of skew adjusters on a given one of the two or more strata until the amount of the alternating current supply noise on the given one of the two or more strata is below a predetermined threshold.

13. The method of claim 8, wherein each of the plurality of clock distribution circuits comprises a power grid having a plurality of sectors, and wherein each of the plurality of voltage droop sensors is located within or proximate to a respective one of the plurality of sectors in the at least some of the two or more strata.

14. The method of claim 8, wherein at least one of the plurality of voltage droop sensors and at least one of the plurality of skew adjusters, both located on a same one of the two or more strata, are used to respectively detect the alternating current supply noise on a different one of the two or more strata and to delay the one or more clock signals on the different one of the two or more strata.

15. A 3D chip stack having two or more strata, the chip stack comprising:

a plurality of power distribution circuits, each being arranged on a respective one of the two or more strata for providing power signals to various locations thereon;

a plurality of clock distribution circuits, each being arranged on the respective one of the two or more strata for providing clock signals to particular locations thereon;

a plurality of voltage droop sensors, one or more being respectively arranged on at least some of the two or more strata for detecting alternating current supply noise in the power signals; and

a plurality of skew adjusters, each being respectively arranged on the at least some of the two or more strata for delaying one or more of the clock signals responsive to an amount of the alternating current supply noise.

16. The 3D chip stack of claim 15, wherein the amount is represented by an amplitude of the alternating current supply noise.

17. The 3D chip stack of claim 15, wherein each of the plurality of voltage droop sensors determines an average amount of the alternating current supply noise over a respective one of the two or more strata.

18. The 3D chip stack of claim 15, wherein each of the plurality of clock distribution circuits comprises a respective clock grid and a plurality of clock buffers.

19. The 3D chip stack of claim 18, wherein each of the plurality of clock buffers comprise a sector clock buffer for driving the respective clock grid on a same one of the two or more strata and a plurality of clock relay buffers.

20. The 3D chip stack of claim 15, wherein each of the plurality of power distribution circuits comprise a respective one of a plurality of power grids for providing the power signals to the various locations thereon.

21. The 3D chip stack of claim 15, wherein a delay provided by the plurality of skew adjusters is adjusted one stratum at a time when the two or more strata comprise at least three strata.

22. The 3D chip stack of claim 15, wherein the plurality of skew adjusters provides a delay to adjust a skew of the one or more clock signals until the amount of the alternating current supply noise is below a predetermined threshold.

23. The 3D chip stack of claim 15, wherein each of the plurality of clock distribution circuits comprise a plurality of sectors, each of the plurality of sectors driven by a sector clock buffer.

24. The 3D chip stack of claim 15, wherein each of the plurality of voltage droop sensors is respectively arranged within or adjacent to a respective one of the plurality of sectors.

25. A method for providing a 3D chip stack having two or more strata with reduced alternating current supply noise, the method comprising:

arranging each of a plurality of power distribution circuits on a respective one of the two or more strata to provide power signals to various locations thereon;

arranging each of a plurality of clock distribution circuits on the respective one of the two or more strata to provide clock signals to particular locations thereon;

respectively arranging one or more of a plurality of voltage droop sensors on at least some of the two or more strata to detect alternating current supply noise in the power signals; and

respectively arranging each of a plurality of skew adjusters on the at least some of the two or more strata to delay one or more of the clock signals responsive to an amount of the alternating current supply noise.