Scalable system for wide area surveillance
First Claim
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1. A controller for a surveillance system, comprising:
- a first port for coupling a first camera;
a second port for coupling a second camera;
a first synchronization logic block coupled to the first port and configured to update a first cycle time register of the first camera coupleable to the first port;
a second synchronization logic block coupled to the second port and configured to update a second cycle time register of the second camera coupleable to the second port;
an image sharing logic block coupled to the synchronization logic block of the first port and the synchronization logic block of the second port;
an image pair-processing logic block coupled to the image sharing logic block;
an information aggregation logic block coupled to the first synchronization logic block and the second synchronization logic block through the image pair-processing logic block and the image sharing logic block;
a synchronization channel connected to a synchronization signal of a synchronization controller and coupled to the synchronization logic blocks; and
an output port coupled to the information aggregation logic block.
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Abstract
According to one embodiment, a controller for a surveillance system includes ports for coupling a camera, synchronization logic blocks coupled to the ports, an information aggregation logic block coupled to the camera ports, and an output port coupled to the information aggregation logic block. According to another embodiment, a method of scaling a surveillance system includes synchronizing a plurality of cameras, capturing images from the synchronized cameras, aggregating at least two processed synchronized images, and processing the aggregated synchronized images.
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Citations
23 Claims
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1. A controller for a surveillance system, comprising:
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a first port for coupling a first camera; a second port for coupling a second camera; a first synchronization logic block coupled to the first port and configured to update a first cycle time register of the first camera coupleable to the first port; a second synchronization logic block coupled to the second port and configured to update a second cycle time register of the second camera coupleable to the second port; an image sharing logic block coupled to the synchronization logic block of the first port and the synchronization logic block of the second port; an image pair-processing logic block coupled to the image sharing logic block; an information aggregation logic block coupled to the first synchronization logic block and the second synchronization logic block through the image pair-processing logic block and the image sharing logic block; a synchronization channel connected to a synchronization signal of a synchronization controller and coupled to the synchronization logic blocks; and an output port coupled to the information aggregation logic block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method comprising:
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generating a synchronization signal comprising a continuous source of isochronous cycle start times; periodically synchronizing cycle time registers of a plurality of cameras according to the synchronization signal; capturing images from the synchronized cameras; aggregating information from at least two synchronized images to main memory of a processor; and the processor processing the aggregated information. - View Dependent Claims (17, 18, 19, 20)
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21. A network of systems for surveillance, comprising:
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at least two subsystems, wherein each subsystem includes; at least two modular controlled cards for a surveillance system wherein each controller card includes a first port for coupling a camera, a second port for coupling a camera, a first synchronization field programmable gate array (FPGA) logic block coupled to the first port and configured to update a cycle time register of a camera coupled to the first port, a second synchronization FPGA logic block coupled to the second port and configured to update a cycle time register of a camera coupled to the second port, an image sharing FPGA logic block coupled to the synchronization FPGA logic block of the first port and the synchronization FPGA logic block of the second port, an image pair-processing FPGA logic block coupled to the image sharing FPGA logic block, an information aggregation FPGA logic block coupled to the output of the image pair-processing FPGA logic block, and an output port coupled to the information aggregation FPGA logic block; a communication channel coupled to the output port of the controller cards; and a chassis supporting the controller cards; a low latency switch coupled to the first system and the second system; a processor coupled to the communication channel; and a synchronization controller coupled to a synchronization channel on the communication channel coupled to at least two synchronization logic blocks on a controller, wherein the synchronization controller outputs a continuous source for isochronous cycle start times onto the synchronization channel. - View Dependent Claims (22, 23)
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Specification