Semiconductor device

• US 8,587,999 B2
• Filed: 11/09/2012
• Issued: 11/19/2013
• Est. Priority Date: 01/15/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/672,973
• Publication Number:
  US 20130099299A1
• Time in Patent Office: 375 Days
• Field of Search: 365/185.08
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other.

Claims

1. A semiconductor device comprising:

semiconductor substrate including a channel formation region and a pair of impurity regions;

a first gate insulating layer over the channel formation region;

a first gate electrode over the gate insulating layer;

a first interlayer insulating layer over the gate electrode;

a source electrode and a drain electrode over the first interlayer insulating layer;

an oxide semiconductor layer adjacent to the source electrode and the drain electrode;

a second gate insulating layer adjacent to the oxide semiconductor layer;

a second gate electrode and an electrode adjacent to the second gate insulating layer; and

a second interlayer insulating layer over the second gate electrode and the electrode,

wherein a capacitor is formed between the electrode and one of the source electrode and the drain electrode, and

wherein the source electrode and the drain electrode have a tapered shape with a taper angle from 30°

to 60°

inclusive.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate is a single crystal semiconductor substrate.

3. The semiconductor device according to claim 1, wherein the other of the source electrode and the drain electrode is electrically connected to a first signal line, and wherein the second gate electrode is electrically connected to a second signal line.

4. The semiconductor device according to claim 1, wherein the electrode is electrically connected to a word line.

5. The semiconductor device according to claim 1, wherein each of the pair of impurity regions is electrically connected to a source-bit line.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is in direct contact with the first interlayer insulating layer.

7. The semiconductor device according to claim 1, wherein the semiconductor device is incorporated in one selected from the group consisting of a laptop computer, a portable information terminal, an e-book reader, a mobile phone, a digital camera, and a television device.

8. A semiconductor device comprising:

a semiconductor substrate including a channel formation region and a pair of impurity regions;

a first gate insulating layer over the channel formation region;

a first gate electrode over the gate insulating layer;

a first interlayer insulating layer over the gate electrode;

a source electrode and a drain electrode over the first interlayer insulating layer;

an oxide semiconductor layer adjacent to the source electrode and the drain electrode;

a second gate insulating layer adjacent to the oxide semiconductor layer;

a second gate electrode and an electrode adjacent to the second gate insulating layer; and

a second interlayer insulating layer over the second gate electrode and the electrode,

wherein the first gate electrode is electrically connected to one of the source electrode and the drain electrode,

wherein a capacitor is formed between the electrode and the one of the source electrode and the drain electrode, and

wherein the source electrode and the drain electrode have a tapered shape with a taper angle from 30°

to 60°

inclusive.

9. The semiconductor device according to claim 8, wherein the semiconductor substrate is a single crystal semiconductor substrate.

10. The semiconductor device according to claim 8, wherein the other of the source electrode and the drain electrode is electrically connected to a first signal line, and wherein the second gate electrode is electrically connected to a second signal line.

11. The semiconductor device according to claim 8, wherein the electrode is electrically connected to a word line.

12. The semiconductor device according to claim 8, wherein each of the pair of impurity regions is electrically connected to a source-bit line.

13. The semiconductor device according to claim 8, wherein the oxide semiconductor layer is in direct contact with the first interlayer insulating layer.

14. The semiconductor device according to claim 8, wherein the semiconductor device is incorporated in one selected from the group consisting of a laptop computer, a portable information terminal, an e-book reader, a mobile phone, a digital camera, and a television device.