Sense amplifier and method for determining values of voltages on bit-line pair

• US 8,588,020 B2
• Filed: 11/16/2011
• Issued: 11/19/2013
• Est. Priority Date: 11/16/2011
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Shi-Wen
• Primary Examiner(s): Myers, Paul R
• Application Number:
  US13/297,362
• Publication Number:
  US 20130124905A1
• Time in Patent Office: 734 Days
• Field of Search: 365/207, 713/500
• US Class Current: 365/207
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock signal and a first voltage on the bit line, so as to delay the clock signal according to the first voltage and to generate a first delay signal accordingly. The second delay chain is electrically connected to a complementary bit line and configured for receiving the clock signal and a second voltage on the complementary bit line, so as to delay the clock signal according to the second voltage and to generate a second delay signal accordingly.

Claims

1. A sense amplifier, comprising:

a first delay chain, electrically connected to a bit line and configured for receiving a clock signal and a first voltage on the bit line, so as to delay the clock signal according to the first voltage and to generate a first delay signal accordingly; and

a second delay chain, electrically connected to a complementary bit line and configured for receiving the clock signal and a second voltage on the complementary bit line, so as to delay the clock signal according to the second voltage and to generate a second delay signal accordingly.

2. The sense amplifier according to claim 1, wherein each of the first delay chain and the second delay chain comprises even inverters.

3. The sense amplifier according to claim 2, wherein each of the inverters of the first delay chain comprises:

a first P-type transistor, a source/drain terminal thereof being electrically connected to a power-supply voltage, and a gate terminal thereof being configured for receiving a read-enable signal;

a second P-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the first P-type transistor, a gate terminal thereof being served as an input terminal of the inverter, and the other source/drain terminal thereof being served as an output terminal of the inverter;

a first N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the second P-type transistor, and a gate terminal thereof being electrically connected to the gate terminal of the second P-type transistor; and

a second N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the first N-type transistor, a gate terminal thereof being configured for receiving the first voltage, and the other source/drain terminal thereof being electrically connected to a reference voltage.

4. The sense amplifier according to claim 3, wherein each of the inverters of the second delay chain comprises:

a first P-type transistor, a source/drain terminal thereof being electrically connected to the power-supply voltage, and a gate terminal thereof being configured for receiving the read-enable signal;

a second P-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the first P-type transistor, a gate terminal thereof being served as an input terminal of the inverter, and the other source/drain terminal thereof being served as an output terminal of the inverter;

a first N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the second P-type transistor, a gate terminal thereof being electrically connected to the gate terminal of the second P-type transistor; and

a second N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the first N-type transistor, a gate terminal thereof being configured for receiving the second voltage, and the other source/drain terminal thereof being electrically connected to the reference voltage.

5. The sense amplifier according to claim 2, wherein each of the inverters of the first delay chain comprises:

a P-type transistor, a source/drain terminal thereof being electrically connected to a power-supply voltage, a gate terminal thereof being served as an input terminal of the inverter, and the other source/drain terminal thereof being served as an output terminal of the inverter;

a first N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the P-type transistor, and a gate terminal thereof being electrically connected to the gate terminal of the P-type transistor; and

a second N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the first N-type transistor, a gate terminal thereof being configured for receiving the first voltage, and the other source/drain terminal thereof being electrically connected to a reference voltage.

6. The sense amplifier according to claim 5, wherein each of the inverter of the second delay chain comprises:

a P-type transistor, a source/drain terminal thereof being electrically connected to the power-supply voltage, a gate terminal thereof being served as an input terminal of the inverter, and the other source/drain terminal thereof being served as an output terminal of the inverter;

a first N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the P-type transistor, and a gate terminal thereof being electrically connected to the gate terminal of the P-type transistor; and

a second N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the first N-type transistor, a gate terminal thereof being configured for receiving the second voltage, and the other source/drain terminal thereof being electrically connected to the reference voltage.

7. The sense amplifier according to claim 2, wherein each of the inverters of the first delay chain comprises:

a first P-type transistor, a source/drain terminal thereof being electrically connected a power-supply voltage, and a gate terminal thereof being configured for receiving the first voltage;

a second P-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the first P-type transistor, a gate terminal thereof being served as an input terminal of the inverter, and the other source/drain terminal thereof being served as an output terminal of the inverter; and

a N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the second P-type transistor, a gate terminal thereof being electrically connected to the gate terminal of the second P-type transistor, and the other source/drain terminal thereof being electrically connected to a reference voltage.

8. The sense amplifier according to claim 7, wherein each of the inverters of the second delay chain comprises:

a first P-type transistor, a source/drain terminal thereof being electrically connected to a power-supply voltage, and a gate terminal thereof being configured for receiving the second voltage;

a second P-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the first P-type transistor, a gate terminal thereof being served as an input terminal of the inverter, and the other source/drain terminal thereof being served as an output terminal of the inverter; and

a N-type transistor, a source/drain terminal thereof being electrically connected to the other source/drain terminal of the second P-type transistor, a gate terminal thereof being electrically connected to the gate terminal of the second P-type transistor, and the other source/drain terminal thereof being electrically connected to the reference voltage.

9. The sense amplifier according to claim 2, further comprising a phase-variation detector, wherein the phase-variation detector has an initial-operation stage and a sensing-operation stage, the sensing-operation stage is after the initial-operation stage;

in the initial-operation stage, the phase-variation detector detects a sequence of phases of the first delay signal and the second delay signal, so as to generate a first detecting result and store the first detecting result;

in the sensing-operation stage, the phase-variation detector detects a sequence of phases of the first delay signal and the second delay signal, so as to generate a second detecting result and store the second detecting result;

when the second detecting result shows that the first delay signal and the second delay signal are in phase, the phase-variation detector outputs a result opposite to the first detecting result;

when the second detecting result shows that the first delay signal and the second delay signal are out of phase, the phase-variation detector outputs the second detecting result.

10. The sense amplifier according to claim 9, wherein the phase-variation detector comprises:

a first D-type flip-flop, having a first data-input terminal, a first data-output terminal and a first clock-input terminal, the first data-input terminal being configured for receiving the first delay signal, and the first clock-input terminal being configured for receiving the second delay signal;

a second D-type flip-flop, having a second data-input terminal, a second data-output terminal and a second clock-input terminal, the second data-input terminal being configured for receiving the second delay signal, and the second clock-input terminal being configured for receiving the first delay signal;

a third D-type flip-flop, having a third data-input terminal, a third data-output terminal and a third clock-input terminal, the third data-input terminal being configured for receiving a signal outputted from the first data-output terminal, the third clock-input terminal being configured for receiving an initial-setting signal, and the initial-setting signal being configured for determining whether the phase-variation detector is in the initial-operation stage or the sensing-operation stage;

a fourth D-type flip-flop, having a fourth data-input terminal, a fourth data-output terminal and a fourth clock-input terminal, the fourth data-input terminal being configured for receiving a signal outputted from the second data-output terminal, and the fourth clock-input terminal being configured for receiving the initial-setting signal;

a first multiplexer, configured for receiving the signal outputted from the first data-output terminal and a signal outputted from the fourth data-output terminal, and outputting one of the signal outputted from the first data-output terminal and the signal outputted from the fourth data-output terminal according to a selecting signal;

a second multiplexer, configured for receiving the signal outputted from the second data-output terminal and a signal outputted from a third data-output terminal, and outputting one of the signal outputted from the second data-output terminal and the signal outputted from the third data-output terminal according to the selecting signal; and

a comparison circuit, configured for receiving the signal outputted from the first data-output terminal, the signal outputted from the second data-output terminal, the signal outputted from the third data-output terminal and the signal outputted from the fourth data-output terminal, and comparing whether the signal outputted from the first data-output terminal and the signal outputted from the second data-output terminal are in phase, so as to output the selecting signal accordingly;

wherein when a comparing result thereof is positive, the comparison circuit employs the selecting signal to control the first multiplexer and the second multiplexer to output the signal outputted from the fourth data-output terminal and the signal outputted from the third data-output terminal respectively to serve as a result opposite to the first detecting result;

when the comparing result is negative, the comparison circuit employs the selecting signal to control the first multiplexer and the second multiplexer to output the signal outputted from the first data-output terminal and the signal outputted from the second data-output terminal to serve as the second detecting result.

11. A method for determining the values of the voltages on a bit-line pair, comprising:

delaying a clock signal according to a first voltage on a bit line and generating a first delay signal accordingly, and delaying the clock signal according to a second voltage on a complementary bit line and generating a second delay signal accordingly; and

determining which one of the first voltage and the second voltage is larger according to a phase relation between the first delay signal and the second delay signal.

12. The method according to claim 11, wherein it determines that the first voltage is larger than the second voltage when a determining result shows that a phase of the first delay chain leads that of the second delay chain;

and it determines that the second voltage is larger than the first voltage when the determining result shows that the phase of the second delay chain leads that of the first delay chain.