Reception circuit, reception method, and signal transfer system

• US 8,588,359 B2
• Filed: 04/09/2010
• Issued: 11/19/2013
• Est. Priority Date: 10/11/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kibune, Masaya
• Primary Examiner(s): Nguyen, Leon-Viet
• Assistant Examiner(s): Hassan, Sarah
• Application Number:
  US12/757,790
• Publication Number:
  US 20100226421A1
• Time in Patent Office: 1,320 Days
• Field of Search: 375/376, 331/11, 331/17
• US Class Current: 375/376
• CPC Class Codes: H03M 1/007 among different resolutions
• CPC Class Codes: H03M 1/182 the feedback signal controlling the reference levels of the analogue/digital converter
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

A reception circuit includes: an AD converter; an equalization circuit that equalizes an output of the AD converter; a determination circuit to which error information is input from the equalization circuit; and a controller that adjusts at least one of resolution and voltage range of the AD converter, in the circuit the determination circuit outputs a control signal to adjust at least one of resolution and voltage range to the controller based on the error information.

Claims

1. A reception circuit, comprising:

an AD converter;

an equalization circuit that equalizes an output of the AD converter;

a determination circuit that determines a value of error information on the basis of an output of the equalization circuit; and

a controller that adjusts at least one of resolution and voltage range of the AD converter, wherein

the determination circuit outputs a control signal to adjust at least one of resolution and voltage range to the controller on the basis of comparison of the value of error information and a predetermined value.

2. The reception circuit according to claim 1, wherein:

the AD converter comprises;

a reference circuit that generates a reference potential;

a core circuit that compares an input voltage with a plurality of divided potentials obtained by dividing the reference potential and outputs a comparison result; and

an encoder that encodes the comparison result; and

the controller adjusts the voltage range of the AD converter by adjusting the reference potential generated by the reference circuit on the basis of the control signal.

3. The reception circuit according to claim 1, wherein:

the AD converter comprises;

a reference circuit that generates a reference potential;

a core circuit that compares an input voltage with a plurality of divided potentials obtained by dividing the reference potential and outputs a comparison result; and

an encoder that encodes the comparison result; and

the controller adjusts the resolution of the AD converter by partially terminating the supply of a clock to a comparator and amplifier of the core circuit and clipping an output when terminating the supply of a clock.

4. The reception circuit according to claim 1, wherein:

the AD converter comprises;

a reference circuit that generates a reference potential;

a core circuit that compares an input voltage with a plurality of divided potentials obtained by dividing the reference potential and outputs a comparison result; and

an encoder that encodes the comparison result; and

the controller adjusts the resolution of the AD converter by partially terminating the supply of a clock to a comparator and an amplifier of the core circuit and clipping an input when terminating the supply of a clock.

5. The reception circuit according to claim 1, wherein:

the AD converter comprises;

a reference circuit that generates a reference potential;

a core circuit that compares an input voltage with a plurality of divided potentials obtained by dividing the reference potential and outputs a comparison result; and

an encoder that encodes the comparison result; and

the controller adjusts the resolution of the AD converter by partially terminating internal computation of the encoder.

6. The reception circuit according to claim 1, wherein:

the AD converter comprises an output bit selector that selects an output bit of the AD converter and clips a bit not to be output; and

the controller adjusts the resolution of the AD converter by controlling the number of bits to be output from the AD converter by the output bit selector.

7. The reception circuit according to claim 1, wherein:

the controller adjusts both the resolution and the voltage range of the AD converter; and

the determination circuit outputs a control signal to adjust both the resolution and the voltage range of the AD converter to the controller.

8. The reception circuit according to claim 1, wherein:

the AD converter has a plurality of sub AD converters of different numbers of bits and a selector that selects an output of the plurality of sub AD converters and outputs the output to the equalization circuit; and

the controller selectively brings the plurality of sub AD converters into an operating state and controls the selection of the selector in accordance with the selected sub AD converter.

9. The reception circuit according to claim 1, having an initialization signal input terminal that receives an initialization signal to specify an initialization period of time, wherein

the determination circuit generates the control signal based on the error information generated from a test signal having a certain pattern input during the initialization period of time.

10. The reception circuit according to claim 1, wherein

the determination circuit generates the control signal by performing feedback control so that an amount of error included in the error information is smaller than a certain threshold value.

11. The reception circuit according to claim 10, wherein:

the certain threshold value has first and second threshold values; and

the first threshold value is used when the amount of error increases at the time of adjustment and the second threshold value is used when the amount of error decreases at the time of adjustment, and the first threshold value is greater than the second threshold value.

12. The reception circuit according to claim 1, comprising a filter that varies the time characteristic to change the resolution and voltage range by the adjustment circuit.

13. The reception circuit according to claim 7, wherein

the determination circuit comprises a table that stores the resolution and voltage range suitable for the amount of error included in the error information, selects the resolution and voltage range from the table in accordance with the amount of error from the equalization circuit, and outputs a control signal to adjust the resolution and voltage range of the AD converter to the controller after setting the selected resolution and voltage range to the AD converter.

14. The reception circuit according to claim 7, wherein

the determination circuit comprises a table that stores the resolution and voltage range suitable for a coefficient of the equalization circuit and selects the resolution and voltage range from the table in accordance with the coefficient of the equalization circuit.

15. The reception circuit according to claim 7, wherein

the determination circuit comprises a table that stores the resolution and voltage range suitable for the amount of error included in the error information and the coefficient of the equalization circuit and selects the resolution and voltage range from the table in accordance with the amount of error included in the error information and the coefficient of the equalization circuit.

16. The reception circuit according to claim 7, wherein

the determination circuit comprises a table that stores an amount of adjustment step of the resolution and voltage range for a coefficient of the equalization circuit, selects the amount of adjustment step of the resolution and voltage range from the table in accordance with the coefficient of the equalization circuit, and makes an adjustment with the selected amount of adjustment step of the resolution and voltage range.

17. The reception circuit according to claim 7, wherein

the determination circuit comprises a difference detection circuit that detects a change in the amount of error included in the error information and in the coefficient of the equalization circuit, and a change amount adjustment part that determines an amount of adjustment step of the resolution and voltage range from the amount of change detected by the difference detection part, and makes an adjustment with the determined amount of adjustment step of the resolution and voltage range.

18. The reception circuit according to claim 1, wherein

the AD converter is a flash type that has a plurality of quantized cells and selects the plurality of quantized cells at irregular intervals when reducing the resolution.

19. A method of controlling a circuit having an AD converter and an equalization circuit, comprising:

making a two-value determination of an output of the AD converter on the basis of a reference value;

calculating a value of error information between a value determined by the two-value determination and the output;

comparing the calculated value of error information with a reference value; and

controlling at least one of the resolution and voltage range of the AD converter on the basis of the result of the comparison.

20. A signal transfer system comprising:

a transmission circuit that transmits a signal;

a transfer line that is connected to the transmission circuit and which transfers the signal; and

a reception circuit that is connected to the transfer line and which receives the transferred signal, wherein

the reception circuit comprises;

an AD converter that converts the received signal into a multi-bit digital signal;

an equalization circuit that equalizes the digital signal output from the AD converter and generates information about a reproduction state indicative of the reproduction state of the received signal; and

an adjustment circuit that adjusts at least one of an input quantization range and resolution of the AD converter based on the information about the reproduction state from the equalization circuit.