Configurable and compact pixel processing apparatus

• US 8,588,542 B1
• Filed: 12/13/2005
• Issued: 11/19/2013
• Est. Priority Date: 12/13/2005
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Takemoto, Sohei, Lin, Shang-Hung
• Primary Examiner(s): Chu, Randolph I
• Application Number:
  US11/300,794
• Time in Patent Office: 2,898 Days
• Field of Search: 382/162, 382/254, 348/453, 348606-624, 348/597, 348/251, 348/254
• US Class Current: 382/260
• CPC Class Codes: H04N 23/80 Camera processing pipelines; Components thereof
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Abstract

An image processing apparatus for processing pixels is disclosed. The image processing apparatus comprises one or more functional blocks adapted to perform a corresponding functional task on the pixels. Further, the image processing apparatus includes one or more line-delay elements for delaying a horizontal scan line of the pixels. A desired processing task, which includes at least one functional task, is performed by configuring each functional block based on an actual number of the line-delay elements used for performing the desired processing task. Each functional block used for performing the desired processing task receives a group of pixels for processing from one or more horizontal scan lines such that the group overlaps another group of pixels for processing from one or more horizontal scan lines by another functional block.

Claims

1. An image processing apparatus for processing pixels, comprising:

a plurality of functional blocks adapted to perform a corresponding functional task on said pixels arranged into horizontal scan lines, wherein said functional blocks operate concurrently on said pixels, wherein a first functional block of said functional blocks operates on a first set of consecutive horizontal scan lines while a second functional block of said functional blocks operates concurrently on a second set of consecutive horizontal scan lines, wherein said first set includes an overlapping portion of consecutive horizontal scan lines with respect to said second set and a non-overlapping portion of consecutive horizontal scan lines with respect to said second set, wherein said second functional block is configured to receive an output of said first functional block; and

a plurality of line-delay elements for delaying a respective horizontal scan line of said pixels.

2. The image processing apparatus as recited in claim 1 wherein said functional task is one of defective pixel concealment, noise filtering, color interpolation, and edge enhancement.

3. The image processing apparatus as recited in claim 1 wherein each functional block further comprises a configurable output.

4. The image processing apparatus as recited in claim 1 wherein a write operation makes available an output of a functional block to another functional block.

5. The image processing apparatus as recited in claim 1 wherein a functional block is bypassed by coupling said configurable input that receives said target pixel to an output of said functional block.

6. The image processing apparatus as recited in claim 1 wherein said horizontal scan lines are consecutive horizontal scan lines, wherein said functional blocks are configured to perform said corresponding functional tasks by using a first subset of said line-delay elements instead of said plurality of line-delay elements, wherein said functional blocks are configured to perform said corresponding functional tasks by using a second subset of said line-delay elements instead of said plurality of line-delay elements, wherein each line-delay element comprises a memory location in a RAM (random acess memory), wherein each functional block comprises a plurality of configurable inputs, wherein for each functional block said configurable inputs are selectively coupled to a subset of said line-delay elements to receive said respective horizontal scan lines of said pixels, wherein for each functional block at least one of said configurable inputs receives said respective horizontal scan line including a target pixel, wherein for each functional block at least one of said configurable inputs receives said respective horizontal scan line including a pixel adjacent to said target pixel, and wherein each subset of said line-delay elements associated with said functional blocks overlaps another subset of said line-delay elements.

7. A method of processing pixels, said method comprising:

providing a plurality of functional blocks, which operate concurrently on said pixels, in an image processing apparatus, each functional block adapted to perform a corresponding functional task on said pixels arranged into horizontal scan lines, wherein a first functional block of said functional blocks operates on a first set of consecutive horizontal scan lines while a second functional block of said functional blocks operates concurrently on a second set of consecutive horizontal scan lines, wherein said first set includes an overlapping portion of consecutive horizontal scan lines with respect to said second set and a non- overlapping portion of consecutive horizontal scan lines with respect to said second set, wherein said second functional block is configured to receive an output of said first functional block; and

providing a plurality of line-delay elements in said image processing apparatus, each line-delay element for delaying a respective horizontal scan line of pixels.

8. The method as recited in claim 7 wherein said functional task is one of defective pixel concealment, noise filtering, color interpolation, and edge enhancement.

9. The method as recited in claim 7 wherein each functional block further comprises a configurable output, wherein said functional blocks are configured to perform said corresponding functional tasks by using a first subset of said line-delay elements instead of said plurality of line-delay elements, wherein said functional blocks are configured to perform said corresponding functional tasks by using a second subset of said line-delay elements instead of said plurality of line-delay elements.

10. The method as recited in claim 7 further comprising:

performing a write operation to make available an output of a functional block to another functional block.

11. The method as recited in claim 7 further comprising:

bypassing a functional block by coupling said input that receives said target pixel to an output of said functional block.

12. The method as recited in claim 7 wherein said horizontal scan lines are consecutive horizontal scan lines, and further comprising:

for each functional block, configuring at least one input to receive said respective horizontal scan line including a target pixel; and

for each functional block, configuring at least one input to receive said respective horizontal scan line including a pixel adjacent to said target pixel, wherein each subset of said line-delay elements associated with said functional blocks overlaps another subset of said line-delay elements.