Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks
First Claim
1. A neuromorphic system comprising:
- a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks, the plurality of synapse blocks comprising a plurality of neuromorphic circuits arranged in a crossbar configuration, each neuromorphic circuit comprising;
a field effect transistor in a diode configuration electrically connected to variable resistance material, the variable resistance material providing a programmable resistance value;
a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks; and
a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.
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Abstract
A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.
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Citations
13 Claims
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1. A neuromorphic system comprising:
a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks, the plurality of synapse blocks comprising a plurality of neuromorphic circuits arranged in a crossbar configuration, each neuromorphic circuit comprising; a field effect transistor in a diode configuration electrically connected to variable resistance material, the variable resistance material providing a programmable resistance value; a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks; and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for implementing an area efficient neuromorphic system, comprising:
electrically connecting a plurality of synapse blocks to a plurality of neuron circuit blocks, the plurality of synapse blocks comprising a plurality of neuromorphic circuits, each neuromorphic circuit implemented by; electrically connecting a field effect transistor in a diode configuration to variable resistance material, the variable resistance material providing a programmable resistance value; electrically connecting a first junction to the variable resistance material and an output of one or more of the neuron circuit blocks; and electrically connecting a second junction to the field effect transistor and an input of one or more of the neuron circuit blocks. - View Dependent Claims (8, 9, 10)
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11. A design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks, the plurality of synapse blocks comprising a plurality of neuromorphic circuits, each neuromorphic circuit comprising; a field effect transistor in a diode configuration electrically connected to variable resistance material, the variable resistance material providing a programmable resistance value; a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks; and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks. - View Dependent Claims (12, 13)
Specification