Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering
First Claim
1. Digital signal processing (“
- DSP”
) block circuitry comprising;
first multiplier circuitry for producing a first plurality of parallel output signals indicative of a first multiplication product of a plurality of parallel multiplicand signals and a plurality of parallel multiplier signals;
first systolic delay circuitry for delaying at least one of (1) the plurality of parallel multiplicand signals and (2) the plurality of parallel multiplier signals by at least one systolic delay time interval;
second multiplier circuitry for producing a second plurality of parallel output signals indicative of a second multiplication product;
adder circuitry for adding the first and second pluralities of output signals and a third plurality of parallel signals indicative of a data value received from a first other instance of said DSP block circuitry;
output register circuitry for registering output signals of the adder circuitry; and
second systolic delay circuitry for delaying outputs of the output register circuitry by at least one of the systolic delay time interval.
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Abstract
Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use (e.g., in multiple instances of the DSP block circuitry on the IC) for implementing finite-impulse-response (“FIR”) digital filters in systolic form. Each DSP block may include (1) first and second multiplier circuitry and (2) adder circuitry for adding (a) outputs of the multipliers and (b) signals chained in from a first other instance of the DSP block circuitry. Systolic delay circuitry is provided for either the outputs of the first multiplier (upstream from the adder) or at least one of the sets of inputs to the first multiplier. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry.
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Citations
20 Claims
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1. Digital signal processing (“
- DSP”
) block circuitry comprising;first multiplier circuitry for producing a first plurality of parallel output signals indicative of a first multiplication product of a plurality of parallel multiplicand signals and a plurality of parallel multiplier signals; first systolic delay circuitry for delaying at least one of (1) the plurality of parallel multiplicand signals and (2) the plurality of parallel multiplier signals by at least one systolic delay time interval; second multiplier circuitry for producing a second plurality of parallel output signals indicative of a second multiplication product; adder circuitry for adding the first and second pluralities of output signals and a third plurality of parallel signals indicative of a data value received from a first other instance of said DSP block circuitry; output register circuitry for registering output signals of the adder circuitry; and second systolic delay circuitry for delaying outputs of the output register circuitry by at least one of the systolic delay time interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
- DSP”
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15. Digital signal processing (“
- DSP”
) block circuitry comprising;first multiplier means for producing a first plurality of parallel output signals indicative of a first multiplication product of a plurality of parallel multiplicand signals and a plurality of parallel multiplier signals; first systolic delay means for delaying at least one of (1) the plurality of parallel multiplicand signals and (2) the plurality of parallel multiplier signals by at least one systolic delay time interval; second multiplier means for producing a second plurality of parallel output signals indicative of a second multiplication product; adder means for adding the first and second pluralities of output signals and a third plurality of parallel signals indicative of a data value received from a first other instance of said DSP block circuitry; output register means for registering output signals of the adder means; and second systolic delay means for delaying outputs of the output register means by at least one of the systolic delay time interval. - View Dependent Claims (16, 17, 18, 19, 20)
- DSP”
Specification