On-die logic analyzer for semiconductor die

• US 8,589,745 B2
• Filed: 12/11/2012
• Issued: 11/19/2013
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zhong, Tina C., Sandri, Jason G., Griesser, Kenneth P., Borger, Lori R.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US13/710,919
• Publication Number:
  US 20130103987A1
• Time in Patent Office: 343 Days
• Field of Search: 714/724, 711/154, 324/762.03, 324/762.05
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/3003 Monitoring arrangements specially adapted to the computing system or computing system component being monitored
• CPC Class Codes: G06F 11/3089 Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466
• CPC Class Codes: G06F 11/364 tracing values on a bus
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a semiconductor die including a first agent and a second agent coupled via an uni-directional interconnect; and

the semiconductor die further including a logic analyzer, the logic analyzer having a trace buffer to store first information communicated from the first agent to the second agent and to store second information communicated from the second agent to the first agent, and to provide the first and second information to an off-die agent, wherein the trace buffer includes a first portion to store transactions from the first agent to the second agent and a second portion to store transactions from the second agent to the first agent.

2. The apparatus of claim 1, wherein the second portion is to be pre-loaded with test content to perform high volume manufacturing (HVM) testing on the apparatus, and the first portion is to store the transactions from the first agent to the second agent during the HVM testing.

3. The apparatus of claim 1, wherein the logic analyzer includes a trigger logic to enable start of capture of a trace into the trace buffer and to stop the trace capture.

4. The apparatus of claim 3, wherein the trigger logic is to enable the trace capture upon occurrence of an event in the semiconductor die, under control of information stored in at least one configuration register of the logic analyzer.

5. The apparatus of claim 2, wherein the second agent further comprises a bus responder to receive signals from the first agent and to transmit signals to the first agent, and a first test interface to couple the logic analyzer to a first off-chip interface via a first serial interconnect.

6. The apparatus of claim 5, wherein the second agent comprises a first selector to select an output from the logic analyzer or the bus responder to communicate to the first agent, wherein the first selector is to provide the test content to the first agent during the HVM testing.

7. The apparatus of claim 1, further comprising an internal observation node module to receive debug signals from a plurality of debug nodes of the semiconductor die and to provide the debug signals and a clock signal to the logic analyzer, the logic analyzer including a pre-storage module to receive the debug signals and the clock signal and to allocate a plurality of the debug signals into a data line with a time stamp for storage into a line of the trace buffer.

8. The apparatus of claim 7, wherein the logic analyzer is to capture the debug signals at a native speed and to output the data line to an off-chip device at a lower speed.

9. The apparatus of claim 1, wherein the trace buffer includes a combining logic having a table to indicate an order of queues to be combined with an active queue.

10. The apparatus of claim 9, wherein the combining logic is to receive activity information regarding the queues from a configuration register of the logic analyzer.

11. The apparatus of claim 1, wherein the logic analyzer includes a pre-memory module to package a plurality of internal node observation signals into a plurality of data blocks corresponding to a data line of a memory of the semiconductor die.

12. The apparatus of claim 11, further comprising a time stamp logic to update a first data block with a time stamp, to correlate events occurring in the apparatus.

13. A method comprising:

receiving information at a customer site from a vendor of a system-on-chip (SoC), the information usable to configure an on-die-logic-analyzer (ODLA) of the SoC and including a test pattern to be stored in a trace buffer of the ODLA;

configuring the ODLA using the information to enable capture of data associated with a system bug;

initiating operation of the SoC and enabling the ODLA to automatically capture the data during the operation at the customer site, including automatically storing first data communicated from a first agent to a second agent of the SoC coupled to the first agent via a uni-directional interconnect, the first data stored in a first storage of the trace buffer dedicated to the first agent;

extracting the data including the first data from the ODLA; and

communicating the data to the SoC vendor.

14. The method of claim 13, further comprising dynamically combining a second storage of the trace buffer with the first storage to store a portion of the first data communicated from the first agent to the second agent.

15. The method of claim 14, further comprising dynamically combining the first and second storages when the first storage is full and the second agent dedicated to the second storage is inactive.

16. The method of claim 13, further comprising extracting the data via a computer system, and placing the data in a file for communication to the SoC vendor via the internet.

17. A system comprising:

a system on a chip (SoC) including a first agent and a second agent coupled via an uni-directional interconnect, and a logic analyzer having a trace buffer including a first portion to store first information communicated from the first agent to the second agent and a second portion to store second information communicated from the second agent to the first agent, wherein the second portion is to be dynamically combined with the first portion when the first portion is full and the second portion is inactive, and to provide the first and second information to an off-die agent; and

a second logic analyzer coupled to the SoC via a second interconnect.

18. The system of claim 17, wherein the first portion is to store transactions from the first agent to the second agent and the second portion is to store transactions from the second agent to the first agent, the second portion to be pre-loaded with test content to perform high volume manufacturing (HVM) testing on the SoC, and the first portion to store the transactions from the first agent to the second agent during the HVM testing.

19. The system of claim 17, wherein the SoC comprises a pre-memory module to package a plurality of internal node observation signals into a plurality of data blocks corresponding to a data line of a memory of the SoC and a time stamp logic to update a first data block of the plurality of data blocks with a time stamp.