Retention based intrinsic fingerprint identification featuring a fuzzy algorithm and a dynamic key

• US 8,590,010 B2
• Filed: 11/22/2011
• Issued: 11/19/2013
• Est. Priority Date: 11/22/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Fainstein, Daniel J., Cestero, Alberto, Iyer, Subramanian S., Kirihata, Toshiaki, Robson, Norman W., Rosenblatt, Sami
• Primary Examiner(s): Mehedi, Morshed
• Assistant Examiner(s): LYNCH, SHARON S
• Application Number:
  US13/302,314
• Publication Number:
  US 20130133031A1
• Time in Patent Office: 728 Days
• Field of Search: 713/193, 713/168, 713/189, 726/9, 726/2, 380/46, 702/57
• US Class Current: 726/2
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 2221/2103 Challenge-response
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/127 Trusted platform modules [TPM]
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

A random intrinsic chip ID generation employs a retention fail signature. A 1^st and 2^nd ID are generated using testing settings with a 1^st setting more restrictive than the 2^nd, creating more fails in the 1^st ID bit string that includes 2^nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1^st ID includes the 2^nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3^rd ID with intermediate condition such that 1^st ID includes 3^rd ID bit string and 3^rd ID includes 2^nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2^nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

Claims

1. A method for identifying a chip having a memory array comprising;

a) using a computer, determining parameters intrinsic to said memory array;

b) generating a window address location of said memory array;

c) selecting a first fail-count target;

d) generating first binary strings using a first bit map by iterating a test on said window address location of said memory array while enabling a feedback to said memory array for controlling a number of first fail-counts until said first fail-count target is reached, wherein said first bit map includes passing and failing memory address locations;

e) selecting a second fail-count target smaller than said first fail-count target;

f) generating second binary strings using a second bit map by iterating a test on said window address location of said memory array while enabling a feedback to said array for controlling the number of second fail-counts until said second fail-count target is reached, wherein said second bit map includes passing and failing memory address locations; and

g) comparing said first binary string to said second binary string, wherein when said first binary string comprises all failing memory addresses of said second binary string, then said first binary string and second binary string become said chip identity (ID).

2. The method as recited in claim 1, further comprising selecting a new window address location of said memory array when said first binary string does not include all of said failing memory addresses of said second binary string.

3. The method as recited in claim 1, wherein said memory array comprises a plurality of cells comprising one transistor and one capacitor, wherein each of said cells stores a charge as a logic 1 to said capacitor prior to generating said first and second bit maps and wherein said stored charge as a logic 1 leaks, generating retention fails in said first and second bit maps.

4. The method as recited in claim 3 further comprises controlling the number of said fail-counts due to said retention fails using a retention pause time or using a word line (WL) low voltage.

5. The method as recited in claim 4, wherein said retention pause time or said WL low voltage are adjusted using a built-in-self test engine detecting retention fails in said first and second bit maps, and a counter detecting a number of retention fails in said first and second bit maps, wherein said number of retention fails is approximately equal to both of said fail-count targets.

6. The method as recited in claim 1 further comprising storing said first binary strings and second binary strings in a database as said ID used for authentication, wherein said authentication is enabled by generating a third binary string with an intermediate fail-count, in which the intermediate fail-count is less than said first fail-count and more than said second fail-count, and wherein said third binary string includes the failing memory addresses in said third binary string, and said third binary string includes the failing memory addresses in said second binary string.

7. The method as recited in claim 6, wherein an intermediate fail-count is changed at each authentication.

8. The method as recited in claim 6, wherein said intermediate fail-count further includes a guard-band to eliminate bit instability near said first and second ID generation boundary.

9. The method as recited in claim 1 wherein said first and second binary strings are enabled by applying two corresponding fixed keys to identify said target of said fail-counts to said first and second binary strings.

10. The method as recited in claim 1, wherein said memory array comprises a plurality of cross-coupled inverter cells, and wherein each of said cells store a logic 1 to flip in one direction and a logic 0 when in an opposite direction.

11. A method for identifying a chip comprising:

a) using a computer, determining parameters intrinsic to said memory array

b) generating a window address location of said memory array;

c) selecting a first fail-count target;

d) generating first binary strings using a first bit map by iterating a test on said window address location of said memory array while enabling a feedback to said memory array for controlling a number of said fail-counts until said first fail-count target is achieved, wherein said first bit map includes passing and failing memory address locations;

e) selecting a second fail-count target smaller than said first fail-count

f) generating second binary strings using a second bit map by iterating a test on said window address location of said memory array while enabling a feedback to said array for controlling the number of said fail-counts until a second fail-count target is obtained, wherein said second bit map includes passing and failing memory address locations; and

g) comparing said first binary string to said second binary string, wherein when said first binary string comprises all failing memory addresses of said second binary string, then said first binary string and second binary string become said chip identity (ID).

12. The method as recited in claim 11, wherein a third ID read from said chip is changed at each consecutive authentication event.

13. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for identifying a chip having a memory array, the method steps comprising:

a) using a computer, determining parameters intrinsic to said memory array;

b) generating a window address location of said memory array;

c) selecting a first fail-count target;

d) generating first binary strings using a first bit map by iterating a test on said window address location of said memory array while enabling a feedback to said memory array for controlling a number of said fail-counts until said first fail-count target is achieved, wherein said first bit map includes passing and failing memory address locations;

e) selecting a second fail-count target smaller than said first fail-count target;

f) generating second binary strings using a second bit map by iterating a test on said window address location of said memory array while enabling a feedback to said array for controlling the number of said fail-counts until a second fail-count target is obtained, wherein said second bit map includes passing and failing memory address locations; and

g) comparing said first binary string to said second ID binary string, wherein when said first binary string comprises all failing memory addresses of said second binary string, then said first binary string and second binary string become said chip identity (ID).