Retention based intrinsic fingerprint identification featuring a fuzzy algorithm and a dynamic key
First Claim
1. A method for identifying a chip having a memory array comprising;
- a) using a computer, determining parameters intrinsic to said memory array;
b) generating a window address location of said memory array;
c) selecting a first fail-count target;
d) generating first binary strings using a first bit map by iterating a test on said window address location of said memory array while enabling a feedback to said memory array for controlling a number of first fail-counts until said first fail-count target is reached, wherein said first bit map includes passing and failing memory address locations;
e) selecting a second fail-count target smaller than said first fail-count target;
f) generating second binary strings using a second bit map by iterating a test on said window address location of said memory array while enabling a feedback to said array for controlling the number of second fail-counts until said second fail-count target is reached, wherein said second bit map includes passing and failing memory address locations; and
g) comparing said first binary string to said second binary string, wherein when said first binary string comprises all failing memory addresses of said second binary string, then said first binary string and second binary string become said chip identity (ID).
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Accused Products
Abstract
A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.
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Citations
13 Claims
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1. A method for identifying a chip having a memory array comprising;
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a) using a computer, determining parameters intrinsic to said memory array; b) generating a window address location of said memory array; c) selecting a first fail-count target; d) generating first binary strings using a first bit map by iterating a test on said window address location of said memory array while enabling a feedback to said memory array for controlling a number of first fail-counts until said first fail-count target is reached, wherein said first bit map includes passing and failing memory address locations; e) selecting a second fail-count target smaller than said first fail-count target; f) generating second binary strings using a second bit map by iterating a test on said window address location of said memory array while enabling a feedback to said array for controlling the number of second fail-counts until said second fail-count target is reached, wherein said second bit map includes passing and failing memory address locations; and g) comparing said first binary string to said second binary string, wherein when said first binary string comprises all failing memory addresses of said second binary string, then said first binary string and second binary string become said chip identity (ID). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for identifying a chip comprising:
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a) using a computer, determining parameters intrinsic to said memory array b) generating a window address location of said memory array; c) selecting a first fail-count target; d) generating first binary strings using a first bit map by iterating a test on said window address location of said memory array while enabling a feedback to said memory array for controlling a number of said fail-counts until said first fail-count target is achieved, wherein said first bit map includes passing and failing memory address locations; e) selecting a second fail-count target smaller than said first fail-count f) generating second binary strings using a second bit map by iterating a test on said window address location of said memory array while enabling a feedback to said array for controlling the number of said fail-counts until a second fail-count target is obtained, wherein said second bit map includes passing and failing memory address locations; and g) comparing said first binary string to said second binary string, wherein when said first binary string comprises all failing memory addresses of said second binary string, then said first binary string and second binary string become said chip identity (ID). - View Dependent Claims (12)
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13. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for identifying a chip having a memory array, the method steps comprising:
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a) using a computer, determining parameters intrinsic to said memory array; b) generating a window address location of said memory array; c) selecting a first fail-count target; d) generating first binary strings using a first bit map by iterating a test on said window address location of said memory array while enabling a feedback to said memory array for controlling a number of said fail-counts until said first fail-count target is achieved, wherein said first bit map includes passing and failing memory address locations; e) selecting a second fail-count target smaller than said first fail-count target; f) generating second binary strings using a second bit map by iterating a test on said window address location of said memory array while enabling a feedback to said array for controlling the number of said fail-counts until a second fail-count target is obtained, wherein said second bit map includes passing and failing memory address locations; and g) comparing said first binary string to said second ID binary string, wherein when said first binary string comprises all failing memory addresses of said second binary string, then said first binary string and second binary string become said chip identity (ID).
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Specification