×

Method of forming low resistance gate for power MOSFET applications

  • US 8,592,277 B2
  • Filed: 09/27/2010
  • Issued: 11/26/2013
  • Est. Priority Date: 02/10/2006
  • Status: Active Grant
First Claim
Patent Images

1. A method of forming a trench gate field effect transistor, the method comprising:

  • forming a trench in a silicon region;

    forming a dielectric layer lining a sidewall of the trench and a bottom surface of the trench;

    forming a first polysilicon layer on the bottom surface of the trench;

    forming a first conductive material layer on an exposed surface of the first polysilicon layer;

    forming a second polysilicon layer on an exposed surface of the first conductive material layer; and

    performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the first conductive material layer to react.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×