Electronic device including a tapered trench and a conductive structure therein and a process of forming the same

• US 8,592,279 B2
• Filed: 12/15/2011
• Issued: 11/26/2013
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Loechelt, Gary H.
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US13/327,422
• Publication Number:
  US 20130153992A1
• Time in Patent Office: 712 Days
• Field of Search: 438/301, 438/194, 438/289, 438/299, 257/402, 257/E21.409, 257/E29.255, 257/337, 257/288, 257/E21.616, 257/E27.06
• US Class Current: 438/301
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of the trench and has a dopant concentration greater than a dopant concentration of the semiconductor layer. In another embodiment, the electronic device can include a conductive structure within a relatively narrower portion of the trench, and a conductive electrode within a relatively wider portion of the trench. In another embodiment, a process of forming the electronic device can include forming a sacrificial plug and may allow insulating layers of different thicknesses to be formed within the trench.

Claims

1. A process of forming an electronic device comprising:

providing a semiconductor layer overlying a substrate and having a primary surface;

patterning the semiconductor layer to define a trench having a tapered portion;

forming a first insulating layer within the tapered portion;

forming a sacrificial plug within the tapered portion;

removing a first portion of the first insulating layer from the tapered portion, wherein the sacrificial plug substantially protects a second portion of the first insulating layer when removing the first portion of the first insulating layer;

removing the sacrificial plug; and

forming a conductive electrode at a location from which the sacrificial plug was removed.

2. The process of claim 1, further comprising forming a second insulating layer after removing the portion of the first insulating layer, wherein the second insulating layer is thinner than the first insulating layer.

3. The process of claim 1, further comprising forming a conductive structure, wherein:

patterning the semiconductor layer comprises forming another portion of the trench, wherein the other portion has substantially vertical sidewalls and is disposed below the tapered portion; and

forming the conductive structure comprises forming the conductive structure within the other portion of the trench before forming the first insulating layer.

4. The process of claim 3, further comprising forming a doped semiconductor region adjacent to the tapered portion, wherein:

forming the doped semiconductor region is performed after forming the conductive structure and before forming the first insulating layer; and

a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface.

5. The process of claim 2, wherein the first and second insulating layers have substantially a same composition.