Silicided device with shallow impurity regions at interface between silicide and stressed liner

• US 8,592,308 B2
• Filed: 07/20/2011
• Issued: 11/26/2013
• Est. Priority Date: 07/20/2011
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ayala, Javier, Lavoie, Christian, Ozcan, Ahmet S.
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US13/186,587
• Publication Number:
  US 20130020616A1
• Time in Patent Office: 860 Days
• Field of Search: 257/288, 257/E21.158, 257/E29.255, 438/658, 438/210, 438/287, 438/222, 438/383, 438/238
• US Class Current: 438/658
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a silicide contact region of a field effect transistor (FET);

forming a shallow impurity region in a top surface of the silicide contact region, wherein at least one of the impurities in said shallow impurity region is one of carbon (C), nitrogen (N), and fluorine (F); and

forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

2. A field effect transistor (FET), comprising:

a gate structure formed over a substrate;

source and drain regions formed in the substrate, adjacent the gate structure

silicide contact regions formed on the gate structure, source and drain regions, the silicide contacts having a shallow impurity region located at a top surface thereof; and

a stressed liner formed over the FET,

wherein the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, and wherein the shallow impurity region comprises one or more impurities, is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region, and wherein at least one of the impurities in said shallow impurity region is one of carbon (C), nitrogen (N), and fluorine (F).

3. A method of forming a semiconductor device, the method comprising:

forming a silicide contact region of a field effect transistor (FET);

forming a shallow impurity region in a top surface of the silicide contact region wherein at least one of the impurities in said shallow impurity region is one of tantalum (Ta), rhenium (Re), molybdenum (Mo), titanium (Ti), niobium (Nb), arsenic (As) or antimony (Sb), and aluminum (Al); and

forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

4. A method of forming a semiconductor device, the method comprising:

forming a silicide contact region of a field effect transistor (FET);

forming a shallow impurity region in a top surface of the silicide contact region wherein the shallow impurity region has an impurity concentration of about 1E15 per cm² or greater; and

forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

5. A method of forming a semiconductor device, the method comprising:

forming a silicide contact region of a field effect transistor (FET);

forming a shallow impurity region in a top surface of the silicide contact region wherein the shallow impurity region has a depth into the silicide contact region from about 5 nanometers to about 10 nanometers from the top surface of the silicide contact region; and

forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

6. A method of forming a semiconductor device, the method comprising:

forming a silicide contact region of a field effect transistor (FET);

forming a shallow impurity region in a top surface of the silicide contact region wherein the shallow impurity region is formed by implantation of the silicide contact region with one or more of carbon, fluorine, and nitrogen; and

forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

7. The method of claim 6, further comprising forming a screen layer over the FET before implantation of the silicide contact region.

8. A method of forming a semiconductor device, the method comprising:

forming a silicide contact region of a field effect transistor (FET);

forming a shallow impurity region in a top surface of the silicide contact region; and

forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region, and wherein the shallow impurity region is further configured to hinder diffusion of germanium within the silicide contact region.

9. A method of forming a semiconductor device, the method comprising:

forming a silicide contact region of a field effect transistor (FET);

forming a shallow impurity region in a top surface of the silicide contact region wherein the shallow impurity region is formed by plasma treatment of the silicide contact region with at least one of methane (CH₄), silane (SiH₄), nitrogen triflouride (NF₃), and nitrogen gas (N₂); and

forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

10. A method of forming a semiconductor device, the method comprising:

forming a silicide contact region of a field effect transistor (FET);

forming a shallow impurity region in a top surface of the silicide contact region wherein the shallow impurity region is formed by cluster implantation of the silicide contact region with at least one of methane (CH₄), silane (SiH₄), nitrogen triflouride (NF₃), and nitrogen gas (N₂); and

forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

11. A field effect transistor (FET), comprising:

a gate structure formed over a substrate;

source and drain regions formed in the substrate, adjacent the gate structure

silicide contact regions formed on the gate structure, source and drain regions, the silicide contacts having a shallow impurity region located at a top surface thereof; and

a stressed liner formed over the FET,

wherein the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, and wherein the shallow impurity region comprises one or more impurities, is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region, and wherein at least one of the impurities in said shallow impurity region is one of tantalum (Ta), rhenium (Re), molybdenum (Mo), titanium (Ti), niobium (Nb), arsenic (As) or antimony (Sb), and aluminum (Al).

12. A field effect transistor (FET), comprising:

a gate structure formed over a substrate;

source and drain regions formed in the substrate, adjacent the gate structure

silicide contact regions formed on the gate structure, source and drain regions, the silicide contacts having a shallow impurity region located at a top surface thereof; and

a stressed liner formed over the FET,

wherein the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, and wherein the shallow impurity region comprises one or more impurities, is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region, and wherein the shallow impurity region has an impurity concentration of about 1E15 per cm² or greater.

13. A field effect transistor (FET), comprising:

a gate structure formed over a substrate;

source and drain regions formed in the substrate, adjacent the gate structure

silicide contact regions formed on the gate structure, source and drain regions, the silicide contacts having a shallow impurity region located at a top surface thereof; and

a stressed liner formed over the FET,

wherein the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, and wherein the shallow impurity region comprises one or more impurities, is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region, and wherein the shallow impurity region has a depth in the silicide contact region from about 5 nanometers to about 10 nanometers from the top surface of the silicide contact region.

14. A field effect transistor (FET), comprising:

a gate structure formed over a substrate;

source and drain regions formed in the substrate, adjacent the gate structure

silicide contact regions formed on the gate structure, source and drain regions, the silicide contacts having a shallow impurity region located at a top surface thereof; and

a stressed liner formed over the FET,

wherein the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, and wherein the shallow impurity region comprises one or more impurities, is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region; and

further comprising a screen layer located over the FET between the shallow impurity region and the stressed liner.