Active matrix substrate and display panel

• US 8,592,811 B2
• Filed: 02/14/2011
• Issued: 11/26/2013
• Est. Priority Date: 05/11/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Suzuki, Masahiko, Chikama, Yoshimasa, Yoshida, Tokuo, Harumoto, Yoshiyuki, Mizuno, Yuuji, Ohta, Yoshifumi, Nakagawa, Okifumi, Miyamoto, Yoshinobu, Yamashita, Tetsuya
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US13/697,106
• Publication Number:
  US 20130207114A1
• Time in Patent Office: 1,016 Days
• Field of Search: None
• US Class Current: 257/43
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting

Abstract

An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).

Claims

1. An active matrix substrate comprising:

a plurality of pixel electrodes arranged in a matrix; and

a plurality of thin film transistors each connected to a corresponding one of the pixel electrodes, and each including a gate electrode provided on an insulating substrate, a gate insulating film covering the gate electrode, a semiconductor layer provided on the gate insulating film and having a channel region overlapping the gate electrode, and a source electrode and a drain electrode of copper or copper alloy provided on the gate insulating film and separated from each other by the channel region of the semiconductor layer,

wherein

the semiconductor layer is formed of an oxide semiconductor and covers the source and drain electrodes,

an interlayer insulating film of a silicon oxide film is provided to cover each of the thin film transistors,

each of the pixel electrodes is provided on the interlayer insulating film, and is connected to the drain electrode of a corresponding one of the thin film transistors via a contact hole formed in the interlayer insulating film and a contact hole formed in the semiconductor layer, and

the contact hole formed in the interlayer insulating film is larger than the contact hole formed in the semiconductor layer as viewed from above, and a step-like portion is provided between an inner wall of the contact hole formed in the interlayer insulating film and an inner wall of the contact hole formed in the semiconductor layer.

3. The active matrix substrate of claim 1, comprising:

an underlying interconnect formed in the same layer in which the gate electrode is provided and formed of the same material as that of the gate electrode; and

an interconnect terminal layer formed in the same layer in which the pixel electrodes are provided, formed of the same material as that of the pixel electrodes, and connected to the underlying interconnect,

wherein

the underlying interconnect and the interconnect terminal layer are connected together via a contact hole formed in the interlayer insulating film and a contact hole formed in the gate insulating film, and

another semiconductor layer of the same material as that of the semiconductor layer and having an annular shape is provided between the gate insulating film and the interlayer insulating film, surrounding the contact hole formed in the gate insulating film and being exposed through the contact hole formed in the interlayer insulating film.

8. The active matrix substrate of claim 1, wherein

the oxide semiconductor is an In—

Ga—

Zn—

O oxide semiconductor layer.

2. An active matrix substrate comprising:

a plurality of pixel electrodes arranged in a matrix;

a plurality of thin film transistors each connected to a corresponding one of the pixel electrodes, and each including a gate electrode provided on an insulating substrate, a gate insulating film covering the gate electrode, a semiconductor layer provided on the gate insulating film and having a channel region overlapping the gate electrode, and a source electrode and a drain electrode of copper or copper alloy provided on the gate insulating film and separated from each other by the channel region of the semiconductor layer;

an underlying interconnect formed in the same layer in which the gate electrode is provided and formed of the same material as that of the gate electrode; and

an interconnect terminal layer formed in the same layer in which the pixel electrodes are provided, formed of the same material as that of the pixel electrodes, and connected to the underlying interconnect,

wherein

the semiconductor layer is formed of an oxide semiconductor and covers the source and drain electrodes,

an interlayer insulating film of a silicon oxide film is provided to cover each of the thin film transistors,

the underlying interconnect and the interconnect terminal layer are connected together via a contact hole formed in the interlayer insulating film and a contact hole formed in the gate insulating film, and

another semiconductor layer of the same material as that of the semiconductor layer and having an annular shape is provided between the gate insulating film and the interlayer insulating film, surrounding the contact hole formed in the gate insulating film and being exposed through the contact hole formed in the interlayer insulating film.

4. The active matrix substrate of claim 2, wherein

the underlying interconnect is a gate line connected to the gate electrode.

5. The active matrix substrate of claim 2, comprising:

a source line formed in the same layer in which the source and drain electrodes are provided, formed of the same material as that of the source and drain electrodes, covered by the semiconductor layer, and connected to the source electrode; and

an interconnect connection layer formed of the same layer in which the pixel electrodes are formed, formed of the same material as that of the pixel electrodes, and connecting the underlying interconnect and the source line together,

wherein

the source line and the interconnect connection layer are connected together via a contact hole formed in the interlayer insulating film and a contact hole formed in the semiconductor layer,

in a connection portion of the source line and the interconnect connection layer, the contact hole formed in the interlayer insulating film is larger than the contact hole formed in the semiconductor layer as viewed from above, and a step-like portion is provided between an inner wall of the contact hole formed in the interlayer insulating film and an inner wall of the contact hole formed in the semiconductor layer,

the underlying interconnect and the interconnect connection layer are connected together via the contact hole formed in the interlayer insulating film and the contact hole formed in the gate insulating film, and

in a connection portion of the underlying interconnect and the interconnect connection layer, the semiconductor layer is provided between the gate insulating film and the interlayer insulating film, surrounding the contact hole formed in the gate insulating film and being exposed through the contact hole formed in the interlayer insulating film.

6. A display panel comprising:

an active matrix substrate and a counter substrate facing each other; and

a display medium layer provided between the active matrix substrate and the counter substrate,

wherein

the active matrix substrate includes

a plurality of pixel electrodes arranged in a matrix, and

a plurality of thin film transistors each connected to a corresponding one of the pixel electrodes, and each including a gate electrode provided on an insulating substrate, a gate insulating film covering the gate electrode, a semiconductor layer provided on the gate insulating film and having a channel region overlapping the gate electrode, and a source electrode and a drain electrode of copper or copper alloy provided on the gate insulating film and separated from each other by the channel region of the semiconductor layer, and

the semiconductor layer is formed of an oxide semiconductor and covers the source and drain electrodes,

an interlayer insulating film of a silicon oxide film is provided to cover each of the thin film transistors,

each of the pixel electrodes is provided on the interlayer insulating film, and is connected to the drain electrode of a corresponding one of the thin film transistors via a contact hole formed in the interlayer insulating film and a contact hole formed in the semiconductor layer, and

the contact hole formed in the interlayer insulating film is larger than the contact hole formed in the semiconductor layer as viewed from above, and a step-like portion is provided between an inner wall of the contact hole formed in the interlayer insulating film and an inner wall of the contact hole formed in the semiconductor layer.

9. The display panel of claim 6, wherein

the oxide semiconductor is an In—

Ga—

Zn—

O oxide semiconductor layer.

7. A display panel comprising:

an active matrix substrate and a counter substrate facing each other; and

a display medium layer provided between the active matrix substrate and the counter substrate,

wherein

the active matrix substrate includes

a plurality of pixel electrodes arranged in a matrix, and

a plurality of thin film transistors each connected to a corresponding one of the pixel electrodes, and each including a gate electrode provided on an insulating substrate, a gate insulating film covering the gate electrode, a semiconductor layer provided on the gate insulating film and having a channel region overlapping the gate electrode, and a source electrode and a drain electrode of copper or copper alloy provided on the gate insulating film and separated from each other by the channel region of the semiconductor layer;

an underlying interconnect formed in the same layer in which the gate electrode is provided and formed of the same material as that of the gate electrode; and

an interconnect terminal layer formed in the same layer in which the pixel electrodes are provided, formed of the same material as that of the pixel electrodes, and connected to the underlying interconnect,

the semiconductor layer is formed of an oxide semiconductor and covers the source and drain electrodes,

an interlayer insulating film of a silicon oxide film is provided to cover each of the thin film transistors,

the underlying interconnect and the interconnect terminal layer are connected together via a contact hole formed in the interlayer insulating film and a contact hole formed in the gate insulating film, and

another semiconductor layer of the same material as that of the semiconductor layer and having an annular shape is provided between the gate insulating film and the interlayer insulating film, surrounding the contact hole formed in the gate insulating film and being exposed through the contact hole formed in the interlayer insulating film.