Integrated circuit device

• US 8,592,831 B2
• Filed: 10/26/2006
• Issued: 11/26/2013
• Est. Priority Date: 02/06/1998
• Status: Expired due to Fees

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Badehi, Avner
• Primary Examiner(s): Graybill, David E
• Application Number:
  US11/588,490
• Publication Number:
  US 20070040180A1
• Time in Patent Office: 2,588 Days
• Field of Search: None
• US Class Current: 257/82
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/02164 : for shielding light, e.g. light blocking layers, cold shields for infrared detectors
• CPC Class Codes: H01L 31/02327 : the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/125 : Composite devices with photosensitive elements and electroluminescent elements within one single body
• CPC Class Codes: H01L 31/186 : Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/483 : Containers
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/52 : Encapsulations
• CPC Class Codes: H01L 33/56 : Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.

Claims

1. A packaged optoelectronic chip comprising:

(a) a die having a face, the die including at least one of a radiation emitter or a radiation receiver adjacent the face;

(b) a transparent packaging layer having a major surface overlying the face of the die and an edge surface bounding the major surface, a first portion of the major surface being exposed at an exterior of the packaged chip; and

(c) an opaque layer covering a second portion of the major surface of the transparent packaging layer adjacent the edge surface, such that the second portion is not exposed at an exterior of the packaged chip.

2. A packaged chip as claimed in claim 1, wherein the opaque layer covers at least a portion of the edge surface of the transparent packaging layer.

3. A packaged chip as claimed in claim 1 wherein the face of the die is a front surface, and the at least one of the radiation emitter or a radiation receiver is disposed adjacent the front surface, and the packaged chip further comprises an insulating layer overlying a rear surface of the die remote from the front surface.

4. A packaged chip as claimed in claim 3 further comprising contacts overlying the insulating layer electrically connected to the die.

7. A packaged chip as claimed in claim 1 wherein said at least one of a radiation emitter or a radiation receiver is an imaging device.

8. A packaged chip as claimed in claim 1 further comprising an array of microlenses operatively associated with the die.

9. A packaged chip as claimed in claim 8 wherein said microlenses are incorporated in said transparent packaging layer.

10. A packaged chip as claimed in claim 1 further comprising an optical grating operatively associated with the die.

11. A packaged chip as claimed in claim 10 wherein said optical grating is incorporated in said transparent packaging layer.

12. A packaged chip as claimed in claim 1 further comprising a wavelength-selective filter operatively associated with the die.

13. A packaged chip as claimed in claim 12 wherein said wavelength-selective filter is incorporated in said transparent packaging layer.

14. A packaged chip as claimed in claim 1, wherein the die has edges extending away from the face, the transparent packaging layer extends beyond at least one of the die edges, and the opaque layer covers at least a portion of the transparent packaging layer between the at least one die edge and the at least one edge of the transparent packaging layer.

15. A packaged chip as claimed in claim 14 wherein the face of the die has a longest dimension and the major surface of the transparent packaging layer has a longest dimension which exceeds the longest dimension of the face of the die by no more than 20%.

16. A packaged chip as claimed in claim 15 wherein the longest dimension of the transparent packaging layer does not exceed the longest dimension of the die by more than 10%.

17. A packaged chip as claimed in claim 15 wherein the longest dimension of the transparent packaging layer does not exceed the longest dimension of the die by more than 5%.

5. A packaged chip as claimed in 1 further comprising contacts electrically connected to the die.

6. A packaged chip as claimed in claim 5 wherein said contacts are solderable contacts.