Embedded MEMS sensors and related methods

• US 8,592,877 B2
• Filed: 06/14/2012
• Issued: 11/26/2013
• Est. Priority Date: 01/27/2009
• Status: Active Grant

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Lakamraju, Narendra V., Venugopal, Sameer M.
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US13/523,755
• Publication Number:
  US 20120256237A1
• Time in Patent Office: 530 Days
• Field of Search: 257/254, 257/415, 257/E29.324
• US Class Current: 257/254
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: G01L 9/005 Non square semiconductive diaphragm
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm

Abstract

Embodiments of embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein.

Claims

1. A semiconductor device, comprising:

a substrate;

a first MEMS array comprising one or more first MEMS devices located over the substrate and configured to short upon exposure to at least a first shock threshold level of a shockwave; and

an electronic device;

wherein;

the electronic device comprises at least one of;

a first display element configured to present information concerning whether the first MEMS array has been exposed to at least the first shock threshold level;

a first conductive path between the display element and the first MEMS array to actuate the display element when the first MEMS array is active after having been exposed to at least the first shock threshold level;

or

a resistor coupled to the first conductive path;

and

the first conductive path comprises;

a first node coupled to a first electrode of the first MEMS array, and configured to couple the first electrode to a power source;

a second node coupled between the display element and a second electrode of the first MEMS array and configured to route power to the display element when the first MEMS array is activated after having been exposed to at least the first shock threshold level; and

a third node coupled between the display element and ground.

2. The semiconductor device of claim 1, wherein:

the substrate comprises a flexible substrate; and

the first MEMS array is fabricated over the flexible substrate.

3. The semiconductor device of claim 1, wherein:

the electronic device is fabricated over the substrate; and

the electronic device is integrated with, and electrically coupled to, the first MEMS array.

4. The semiconductor device of claim 1, wherein:

the resistor comprises a pull down resistor coupled between the second and third nodes of the first conductive path; and

the first display element comprises an electrophoretic display element.

5. The semiconductor device of claim 1, wherein:

at least a first MEMS device of the one or more first MEMS devices comprises;

a conductive base located over the substrate; and

a conductive membrane movably suspended over the conductive base.

6. The semiconductor device of claim 5, wherein:

the conductive membrane is configured to be deformed towards the conductive base by the shockwave such as to remain in permanent contact with the conductive base after being exposed to at least the first shock threshold level.

7. The semiconductor device of claim 5, further comprising:

a common metallic layer over the substrate; and

at least one transistor fabricated over the flexible substrate and electrically coupled to the first MEMS device;

wherein the common metallic layer comprises;

the conductive base of the first MEMS device; and

a gate of the at least one transistor.

8. The semiconductor device of claim 5, wherein:

the first MEMS device comprises;

a sacrificial compartment between the conductive membrane and the conductive base.

9. The semiconductor device of claim 8, wherein:

the substrate comprises at least one of a PEN material, a PET material, a PES material, a polyimide, a polycarbonate, a cyclic olefin copolymer, or a liquid crystal polymer;

the conductive membrane comprises at least one of a chromium material, a silver material, an aluminum material, a titanium material, or a copper material;

the conductive membrane comprises approximately 5 openings to approximately 20 openings into the sacrificial compartment;

the one or more MEMS devices comprise circular perimeters with radii of approximately 50 micrometers to approximately 250 micrometers;

the sacrificial compartment defines an air gap of approximately 0.08 microns to approximately 2 microns between the conductive membrane and the conductive base; and

the conductive membrane is substantially circular.

10. The semiconductor device of claim 5, further comprising:

a wall structure located over at least one of;

the conductive base;

or

the substrate;

wherein the conductive membrane is supported at a perimeter of the conductive membrane by the wall structure.

11. The semiconductor device of claim 10, wherein:

the wall structure circumscribes a perimeter of the first MEMS device and comprises at least one of;

one or more dielectric layers;

or

an amorphous silicon layer.

12. The semiconductor device of claim 5, wherein:

the first MEMS device comprises a first sensitivity for the first shock threshold level; and

the first sensitivity is determined by at least one of;

a thickness of an air gap between the conductive membrane and the conductive base;

a diameter of the conductive membrane;

a thickness of the conductive membrane;

a rigidity of the conductive membrane;

or

a material of the conductive membrane.

13. The semiconductor device of claim 12, wherein:

each of the one or more MEMS devices of the first MEMS array comprises the first sensitivity.

14. The semiconductor device of claim 12, further comprising:

a second MEMS device comprising;

a second conductive base;

a second conductive membrane movably suspended over the second conductive base; and

a second sensitivity to a second shock threshold level different from the first shock threshold level.

15. The semiconductor device of claim 14, further comprising:

a second display element; and

a second conductive path through the second MEMS device to the second display element;

wherein;

the first display element is integrated with, and electrically coupled to, the first MEMS device;

the second display element is integrated with, and electrically coupled to, the second MEMS device;

the conductive membrane is configured to permanently short with the conductive base after exposure to at least the first shock threshold level to complete the first conductive path to the first display element; and

the second conductive membrane is configured to permanently short with the second conductive base after exposure to at least the second shock threshold level to complete the second conductive path to the second display element.

16. The semiconductor device of claim 15, further comprising:

a plurality of MEMS devices responsive to a plurality of shock threshold levels;

a plurality of display elements coupled to respective ones of the plurality of MEMS devices; and

a thermometer code display comprising the plurality of display elements;

wherein;

the plurality of MEMS devices comprises at least the first MEMS device and the second MEMS device;

the plurality of shock threshold levels comprises the first shock threshold level and second shock threshold level;

the plurality of display elements comprises the first and second display elements; and

the thermometer code display is configured to indicate exposure of the plurality of MEMS devices to one or more of the plurality of shock threshold levels via a thermometer code represented by the plurality of display elements.

17. The semiconductor device of claim 14, wherein:

the first MEMS array comprises the second MEMS device.

18. The semiconductor device of claim 14, further comprising:

a second MEMS array located over the substrate;

wherein the second MEMS array comprises the second MEMS device.

19. The semiconductor device of claim 14, further comprising:

a second substrate; and

a second MEMS array located over the substrate;

wherein the second MEMS array comprises the second MEMS device.

20. A semiconductor device, comprising:

a substrate;

a first MEMS array comprising one or more first MEMS devices located over the substrate and configured to short for registering exposure to at least a first shock threshold level of a shockwave;

an electronic device integrated with the substrate and the first MEMS array;

a second MEMS device comprising;

a second conductive base; and

a second conductive membrane movably suspended over the second conductive base;

and

a second display element integrated with, and electrically coupled to, the second MEMS device;

wherein;

the substrate comprises a flexible substrate;

at least a first MEMS device of the one or more first MEMS devices comprises;

a first conductive base located over the substrate;

a first sacrificial compartment located over the first conductive base and bounded by a compartment wall; and

a first conductive membrane movably suspended over the first conductive base by the compartment wall;

the first conductive membrane is configured to be deformed by the shockwave to permanently short with the first conductive base after being exposed to at least the first shock threshold level;

the electronic device comprises;

a first display element; and

a first conductive path between the display element and the first MEMS array to source power to the display element when the first conductive membrane and the first conductive base of the first MEMS device are shorted together;

the second conductive membrane is configured to short with the second conductive base after being exposed to at least a second shock threshold level to source power to the second display element;

the substrate comprises at least one of a PEN material, a PET material, a PES material, a polyimide, a polycarbonate, a cyclic olefin copolymer, or a liquid crystal polymer;

the first conductive membrane comprises at least one of a chromium material, a silver material, an aluminum material, a titanium material, or a copper material;

the first conductive membrane comprises between approximately 5 openings to approximately 20 openings into the sacrificial compartment;

the first MEMS device comprises a circular perimeter with a radius of between approximately 50 micrometers to approximately 250 micrometers;

the first sacrificial compartment defines a first air gap of approximately 0.08 microns to approximately 2 microns between the first conductive membrane and the first conductive base;

the first conductive membrane is substantially circular;

the first MEMS device comprises a first sensitivity for the first shock threshold level, the first sensitivity being established by at least one of;

a thickness of the first air gap;

a diameter of the first conductive membrane;

a thickness of the first conductive membrane;

a rigidity of the first conductive membrane;

or

a material of the first conductive membrane;

the second MEMS device comprises a second sensitivity for the second shock threshold level different from the first shock threshold level; and

the first and second display elements are arranged to present a thermometer code indicative of a peak shock threshold level exposure.