Method for manufacturing semiconductor device

• US 8,592,879 B2
• Filed: 08/30/2011
• Issued: 11/26/2013
• Est. Priority Date: 09/13/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi, Sasagawa, Shinya, Ishizuka, Akihiro
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US13/220,736
• Publication Number:
  US 20120061670A1
• Time in Patent Office: 819 Days
• Field of Search: None
• US Class Current: 257/288
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.

Claims

1. A semiconductor device comprising:

an insulating film having a projection;

a gate electrode over the projection, wherein the gate electrode covering at least a top surface of the projection;

a gate insulating film over the gate electrode;

a source electrode and a drain electrode over the gate insulating film, wherein the source electrode and the drain electrode do not overlap with the top surface of the projection; and

an oxide semiconductor film over the gate insulating film, wherein the oxide semiconductor film is in contact with the source electrode and the drain electrode.

2. The semiconductor device according to claim 1, wherein the source electrode and the drain electrode are provided over the oxide semiconductor film.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor film is provided over the source electrode and the drain electrode.

4. The semiconductor device according to claim 1, wherein a root-mean-square roughness of a surface of the gate insulating film is less than or equal to 1 nm in a region which overlaps with the top surface of the projection of the insulating film.

5. The semiconductor device according to claim 1, wherein a width of the gate electrode in a channel length direction is greater than or equal to 20 nm and less than or equal to 2000 nm.

6. An electronic device comprising a semiconductor device according to claim 1.

7. A semiconductor device comprising:

an insulating film having a projection;

a gate electrode covering the projection;

a gate insulating film over the gate electrode;

a source electrode and a drain electrode over the gate insulating film, wherein the source electrode and the drain electrode do not overlap with a top surface of the projection; and

an oxide semiconductor film over the gate insulating film, wherein the oxide semiconductor film is in contact with the source electrode and the drain electrode,

wherein the gate electrode overlaps with the source electrode and the drain electrode.

8. The semiconductor device according to claim 7, further comprising a conductive layer between the top surface of the projection and the gate electrode,

wherein part of the gate electrode is in contact with the insulating film.

9. The semiconductor device according to claim 7, wherein the source electrode and the drain electrode are provided over the oxide semiconductor film.

10. The semiconductor device according to claim 7, wherein the oxide semiconductor film is provided over the source electrode and the drain electrode.

11. The semiconductor device according to claim 7, wherein a root-mean-square roughness of a surface of the gate insulating film is less than or equal to 1 nm in a region which overlaps with the top surface of the projection of the insulating film.

12. The semiconductor device according to claim 7, wherein a width of the gate electrode in a channel length direction is greater than or equal to 20 nm and less than or equal to 2000 nm.

13. An electronic device comprising a semiconductor device according to claim 7.

14. A semiconductor device comprising:

an insulating film having a projection;

a gate electrode over the projection, wherein the gate electrode covering at least a top surface of the projection;

a gate insulating film over the gate electrode;

a source electrode and a drain electrode over the gate insulating film, wherein the source electrode and the drain electrode do not overlap with the top surface of the projection; and

an oxide semiconductor film over the gate insulating film, wherein the oxide semiconductor film is in contact with the source electrode and the drain electrode,

wherein the oxide semiconductor film comprises crystals whose c-axes are aligned.

15. The semiconductor device according to claim 14, wherein the oxide semiconductor film has a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film.

16. The semiconductor device according to claim 14, wherein the source electrode and the drain electrode are provided over the oxide semiconductor film.

17. The semiconductor device according to claim 14, wherein the oxide semiconductor film is provided over the source electrode and the drain electrode.

18. The semiconductor device according to claim 14, wherein the gate electrode overlaps with the source electrode and the drain electrode.

19. The semiconductor device according to claim 14, wherein a root-mean-square roughness of a surface of the gate insulating film is less than or equal to 1 nm in a region which overlaps with the top surface of the projection of the insulating film.

20. The semiconductor device according to claim 14, wherein a width of the gate electrode in a channel length direction is greater than or equal to 20 nm and less than or equal to 2000 nm.

21. An electronic device comprising a semiconductor device according to claim 14.