Vertical gated access transistor

• US 8,592,898 B2
• Filed: 10/13/2011
• Issued: 11/26/2013
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US13/272,679
• Publication Number:
  US 20120049246A1
• Time in Patent Office: 775 Days
• Field of Search: 257/330, 257/331, 257/332, 257/391, 257/500
• US Class Current: 257/332
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed while the second region of the substrate is masked.

Claims

1. An integrated circuit comprising:

a semiconductor substrate having an array portion and a logic portion;

at least one U-shaped semiconductor structure formed in the substrate array portion, the semiconductor structure comprising a first source/drain region positioned atop a first pillar, a second source/drain region positioned atop a second pillar, and a U-shaped channel connecting the first and second source/drain regions, wherein the U-shaped channel is contiguous with the semiconductor substrate, and wherein the first and second pillars are in the substrate array portion;

a gate electrode formed in the substrate array portion and adjacent sidewalls of the U-shaped semiconductor structure and between the first and second pillars; and

at least one transistor device formed over the substrate logic portion, the transistor device including a gate dielectric layer and a gate material, wherein the gate dielectric layer is elevated with respect to the first and second source/drain regions.

2. The apparatus of claim 1, wherein the at least one transistor device is a planar transistor.

3. The apparatus of claim 1, wherein a first U-shaped semiconductor structure is separated from a second U-shaped semiconductor structure by a deep trench, wherein the deep trench is deeper than a shallow trench that separates the first pillar from the second pillar, the deep trench being filled with an insulating material.

4. The apparatus of claim 1, further comprising a dielectric spacer formed adjacent to a vertical sidewall of the at least one transistor device.

5. The apparatus of claim 4, wherein the spacer has a width that is greater than or equal to half of a width of the first pillar.

6. The apparatus of claim 1, wherein the gate electrode comprises a conductive, elongate spacer formed adjacent to the U-shaped semiconductor structure.

7. The apparatus of claim 6, wherein the elongate spacer is formed in an intermediate-depth trench that is deeper than a shallow trench that separates the first pillar from the second pillar.

8. The apparatus of claim 7, wherein the gate electrode between the first and second pillar connects the elongate spacer with another elongate spacer adjacent an opposite sidewall of the U-shaped semiconductor structure.

9. The apparatus of claim 1, wherein the at least one transistor device does not include an insulating cap layer formed thereover.

10. The apparatus of claim 1, further comprising:

a capacitor formed over the first source/drain region; and

an insulated bit line formed over the second source/drain region.