Stacked NMOS DC-to-DC power conversion

• US 8,593,128 B2
• Filed: 05/21/2012
• Issued: 11/26/2013
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: R2 Semiconductor, Inc.
• Original Assignee: R2 Semiconductor, Inc.
• Inventors: Burns, Lawrence M., Fisher, David
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Finch, III, Fred E
• Application Number:
  US13/476,170
• Publication Number:
  US 20120229102A1
• Time in Patent Office: 554 Days
• Field of Search: 323/224, 323/282, 323/288
• US Class Current: 323/288
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver

Abstract

Another embodiment includes a voltage regulator. The voltage regulator includes a series switch element connected between a first voltage supply and a common node, the series switch element comprising an NMOS series switching transistor, a shunt switch element connected between the common node and a second voltage supply, the shunt switch element comprising an NMOS shunt switching transistor. The voltage regulator further includes means for closing the series switch element during a first period by applying a switching gate voltage to a gate of the NMOS series switch transistor of the series switch element, wherein the switching gate voltage has a voltage potential of at least a threshold voltage greater than a voltage potential of the common node, means for closing the shunt switch element during a second period, the shunt switch element comprising an NMOS shunt switching transistor.

Claims

1. A method of generating a regulated voltage, comprising:

generating the regulated voltage through controlled closing and opening of a series switch element and a shunt switch element, the series switch element being connected between a first voltage supply and a common node, and the shunt switch being connected between the common node and a second supply voltage, comprising;

closing the series switch element during a first period, the series switch element comprising an NMOS series switching transistor, the closing of the series switch element comprising;

applying a switching gate voltage to a gate of the NMOS series switch transistor of the series switch element, wherein the switching gate voltage has a voltage potential of at least a threshold voltage greater than a voltage potential of the common node;

closing the shunt switch element during a second period, the shunt switch element comprising an NMOS shunt switching transistor; and

closing a switch that provides a conductive path between a linear regulator and a buffer amplifier of the series switch element, during the second period;

wherein the series switch element further comprises an NMOS series protection transistor stacked with the NMOS series switching transistor, and the shunt switch element further comprises an NMOS shunt protection transistor stacked with the NMOS shunt switching transistor, and further comprising;

closing the series switch element during the first period;

applying a second switching gate voltage to the NMOS series protection transistor; and

charging a floating capacitor during the second period, wherein the floating capacitor is coupled between the common node and a gate of the NMOS series protection transistor, and aids in control of the second switching gate voltage.

2. The method of claim 1, wherein the switch providing the conductive path between the linear regulator and the buffer amplifier of the series switch element comprises a series combination of a switching transistor and a protection transistor.

3. The method of claim 1, wherein the closing the series switch element during the first period further comprises applying the second switching gate voltage to the NMOS series protection transistor, wherein the second switching gate voltage has a voltage potential of less than the first supply voltage plus a maximum DC (direct current) voltage rating of the NMOS series switching transistor, and greater than the voltage potential of the first voltage supply plus the threshold voltage.

4. The method of claim 1, wherein the switch is turned on when the shunt switch element is closed.

5. The method of claim 1, wherein charging the floating capacitor during the second period comprises:

turning on at least a pair of bootstrapping transistors that provide a conductive path between a linear regulator and the floating capacitor.

6. The method of claim 1, wherein the floating capacitor provides a voltage that is higher than the first supply voltage to the switching gate voltage when transitioning to the first period upon closing the series switch element.

7. The method of claim 1, wherein closing the shunt switch element of the second period further comprises:

applying a third switching gate voltage to a gate of the NMOS shunt protection transistor of shunt switch element, wherein the third switching gate voltage has a voltage potential of less than the second supply voltage plus a maximum DC (direct current) voltage rating of the NMOS series switching transistor, and greater than the voltage potential of the first voltage supply minus the maximum DC (direct current) voltage rating of the NMOS series switching transistor.

8. The method of claim 1, further comprising generating the switching gate voltage by level-shifting a control voltage.

9. The method of claim 8, wherein level shifting the control voltage comprises referencing the switching gate voltage to the voltage potential of the common node.

10. The method of claim 1, further comprising voltage-spike-protecting the regulated voltage with voltage spike protection circuitry, wherein the voltage spike protection circuitry comprises a dissipative resistance and a charge-storage circuit.

11. The method of claim 1, wherein the series switch element and the shunt switch element form switching blocks, and each switching block comprises a plurality of switching block segments, and further comprising voltage-spike-protecting the regulated voltage with voltage spike protection circuitry, wherein and at least a portion of the voltage spike protection circuitry is located between the plurality of switching block segments.

12. A method of generating a regulated voltage, comprising:

generating the regulated voltage through controlled closing and opening of a series switch element and a shunt switch element, the series switch element being connected between a first voltage supply and a common node, and the shunt switch being connected between the common node and a second supply voltage, comprising;

closing the series switch element during a first period, the series switch element comprising an NMOS series switching transistor, the closing of the series switch element comprising;

applying a switching gate voltage to a gate of the NMOS series switch transistor of the series switch element, wherein the switching gate voltage has a voltage potential of at least a threshold voltage greater than a voltage potential of the common node;

closing the shunt switch element during a second period, the shunt switch element comprising an NMOS shunt switching transistor; and

closing a switch that provides a conductive path between a linear regulator and a buffer amplifier of the series switch element, during the second period;

wherein the series switch element and the shunt switch element form switching blocks, and each switching block comprises a plurality of switching block segments, and further comprising voltage-spike-protecting the regulated voltage with voltage spike protection circuitry, wherein the voltage spike protection circuitry comprises a plurality of charge-storage circuit elements, wherein each charge-storage circuit segment of the spike protection circuit is physically closer to the switching block segment it protects than any other switching block segment.

13. A voltage regulator comprising:

a series switch element connected between a first voltage supply and a common node, the series switch element comprising an NMOS series switching transistor;

a shunt switch element connected between the common node and a second voltage supply, the shunt switch element comprising an NMOS shunt switching transistor; and

a first driver operative to close the series switch element during a first period by applying a switching gate voltage to a gate of the NMOS series switch transistor of the series switch element, wherein the switching gate voltage has a voltage potential of at least a threshold voltage greater than a voltage potential of the common node;

a second driver operative to close the shunt switch element during a second period, the shunt switch element comprising an NMOS shunt switching transistor; and

a switch that is operative to provide a conductive path between a linear regulator and a buffer amplifier of the series switch element, during the second period;

wherein the series switch element further comprises an NMOS series protection transistor stacked with the NMOS series switching transistor, and the shunt switch element further comprises an NMOS shunt protection transistor stacked with the NMOS shunt switching transistor, and wherein first driver operative to close the series switch element during the first period comprises the first driver being operative to;

apply a second switching gate voltage to the NMOS series protection transistor; and

charge a floating capacitor during the second period, wherein the floating capacitor is coupled between the common node and a gate of the NMOS series protection transistor, and aids in control of the second switching gate voltage.

14. The voltage regulator of claim 13, wherein the switch comprises a series combination of a switching transistor and a protection transistor.

15. The voltage regulator of claim 13, wherein

applying a second switching gate voltage to the NMOS series protection transistor, includes the second switching gate voltage having a voltage potential of less than the first supply voltage plus a maximum DC (direct current) voltage rating of the NMOS series switching transistor, and greater than the voltage potential of the first voltage supply plus the threshold voltage.

16. The voltage regulator of claim 13, wherein the floating capacitor provides a voltage that is higher than the first supply voltage to the switching gate voltage when transitioning to the first period upon closing the series switch element.

17. The voltage regulator of claim 16, further comprising a level shifter for generating the switching gate voltage by level-shifting a control voltage, wherein level shifting the control voltage comprises referencing the switching gate voltage to the voltage potential of the common node.

18. The voltage regulator of claim 13, further comprising a charge-storage circuit between the first voltage supply and the second voltage supply, wherein the charge-storage circuit comprises capacitive elements that are disposed on a same integrated circuit as the series switch element and the shunt switch element, adjacent to each of the series switch element and the shunt switch element, the capacitive elements being located on opposing sides of each of the series switch element and the shunt switch element.