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Phase locked loop (PLL) with multi-phase time-to-digital converter (TDC)

  • US 8,593,189 B1
  • Filed: 01/31/2013
  • Issued: 11/26/2013
  • Est. Priority Date: 01/31/2013
  • Status: Active Grant
First Claim
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1. A multi-phase time-to-digital converter (TDC) for a phase locked loop (PLL), comprising:

  • a first phase finder configured to generate a first fractional phase signal of a multi-phase variable clock (CKV) signal based on at least one of the multi-phase CKV signal or a reference frequency (FREF) signal, the multi-phase CKV signal associated with one or more clock signals and one or more corresponding phases;

    a phase predictor configured to generate at least one of;

    a phase select (QSEL) signal associated with a fractional frequency command word (FCW) signal based on at least one of a FCW signal or a phase reference (PHR) signal;

    ora multi-phase CKV select (CKVSEL) signal corresponding to a clock signal of the one or more clock signals and a phase of the one or more corresponding phases based on at least one of the multi-phase CKV signal or the QSEL signal;

    a second phase finder configured to generate a second fractional phase signal of the multi-phase CKV signal based on at least one of the CKVSEL signal or the QSEL signal; and

    a phase switch configured to select at least one of the first fractional phase signal or the second fractional phase signal based on a phase error (PHE) signal.

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