Phase locked loop (PLL) with multi-phase time-to-digital converter (TDC)

• US 8,593,189 B1
• Filed: 01/31/2013
• Issued: 11/26/2013
• Est. Priority Date: 01/31/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Kuang-Kai, Kuo, Feng Wei, Chen, Huan-Neng, Hsiung, Lee Tsung, Liao, Hsien-Yuan, Staszewski, Robert Bogdan
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/755,159
• Time in Patent Office: 299 Days
• Field of Search: 327/147, 327/156
• US Class Current: 327/156
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03M 1/50 with intermediate conversion to time interval H03M1/64 takes precedence

Abstract

One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal.

Claims

1. A multi-phase time-to-digital converter (TDC) for a phase locked loop (PLL), comprising:

a first phase finder configured to generate a first fractional phase signal of a multi-phase variable clock (CKV) signal based on at least one of the multi-phase CKV signal or a reference frequency (FREF) signal, the multi-phase CKV signal associated with one or more clock signals and one or more corresponding phases;

a phase predictor configured to generate at least one of;

a phase select (QSEL) signal associated with a fractional frequency command word (FCW) signal based on at least one of a FCW signal or a phase reference (PHR) signal;

or

a multi-phase CKV select (CKVSEL) signal corresponding to a clock signal of the one or more clock signals and a phase of the one or more corresponding phases based on at least one of the multi-phase CKV signal or the QSEL signal;

a second phase finder configured to generate a second fractional phase signal of the multi-phase CKV signal based on at least one of the CKVSEL signal or the QSEL signal; and

a phase switch configured to select at least one of the first fractional phase signal or the second fractional phase signal based on a phase error (PHE) signal.

2. The multi-phase time-to-digital converter (TDC) of claim 1, the first phase finder comprising:

a first flip flop (FF) connected to a FREF line and a multi-phase CKV line;

a second FF connected to the FREF line and the multi-phase CKV line;

a third FF connected to the FREF line and the multi-phase CKV line;

a fourth FF connected to the FREF line and the multi-phase CKV line;

an AND gate comprising a first input, a second inverted input, and an output;

the first input of the AND gate connected to an output of the third FF; and

the second inverted input of the AND gate connected to an output of the second FF;

an OR gate comprising a first inverted input, a second input, and an output;

the first inverted input of the OR gate connected to an output of the fourth FF; and

the second input of the OR gate connected to the output of the AND gate; and

an inverter comprising an input and an output, the input of the inverter connected to the output of the third FF, the output of the inverter associated with a second bit for the first fractional phase signal, the output of the OR gate associated with a first bit for the first fractional phase signal.

3. The multi-phase time-to-digital converter (TDC) of claim 1, the phase predictor comprising:

a phase forward component configured to generate the QSEL signal based on at least one of the FCW signal or the PHR signal; and

a multiplexer (MUX) configured to generate the CKVSEL signal by selecting at least one of the one or more clock signals and corresponding phases associated with CKV based on the QSEL signal.

4. The multi-phase time-to-digital converter (TDC) of claim 1, the second phase finder comprising:

one or more time delay units, a first time delay unit of the one or more time delay units comprising;

a first inverter comprising an input and an output, the input of the first inverter connected to at least one of a CKVSEL line or an output of a second inverter of a second time delay unit; and

a first flip flop (FF) comprising an output, the first FF connected to at least one of the CKVSEL line, the output of the second inverter, or a FREF line;

a thermometer decoder connected to the output of the first FF;

a time phase converter connected to the thermometer decoder;

a shift register connected to a QSEL line; and

an adder component connected to the timer phase converter and the shift register.

5. The multi-phase time-to-digital converter (TDC) of claim 4, the thermometer decoder configured to determine a time difference between the FREF signal and the CKVSEL signal.

6. The multi-phase time-to-digital converter (TDC) of claim 4, the second phase finder configured to drive the phase switch when the PHE signal is greater than at least about ninety degrees.

7. The multi-phase time-to-digital converter (TDC) of claim 4, the first phase finder configured to drive the phase switch when the PHE signal is less than at least about ninety degrees.

8. The multi-phase time-to-digital converter (TDC) of claim 1, the phase switch comprising:

an adder component connected to a PHE line;

a flip flop (FF) connected to an output of the adder component, an output of the FF connected to the adder component;

a comparator connected to the output of the FF; and

a multiplexer (MUX) connected to an output of the comparator.

9. The multi-phase time-to-digital converter (TDC) of claim 8, the MUX configured to select at least one of the first fractional phase signal or the second fractional phase signal based on the output of the comparator.

10. The multi-phase time-to-digital converter (TDC) of claim 8, the MUX connected to at least one of a first fractional phase line or a second fractional phase line.

11. A phase locked loop (PLL), comprising:

an accumulator component;

an adder component connected to the accumulator component;

a loop filter connected to the adder component;

a digitally controlled oscillator (DCO) connected to the loop filter;

a sigma delta modulation component connected to at least one of the DCO or the loop filter;

a counter component connected to at least one of the DCO or the adder component; and

a multi-phase time-to-digital converter (TDC), comprising;

a first phase finder connected to the DCO;

a phase predictor connected to the DCO;

a second phase finder connected to the phase predictor; and

a phase switch connected to at least one of the first phase finder, the second phase finder, or the adder component.

12. The phase locked loop (PLL) of claim 11, an output of the DCO connected to an input of at least one of the first phase finder or the phase predictor, the DCO configured to generate a multi-phase variable clock (CKV) signal.

13. The phase locked loop (PLL) of claim 11, an output of the phase switch connected to an input of the adder component.

14. The phase locked loop (PLL) of claim 11, the phase switch configured to disable the second phase finder when the first phase finder is enabled.

15. The phase locked loop (PLL) of claim 11, the phase switch configured to enable the second phase finder when the first phase finder is disabled.

16. The phase locked loop (PLL) of claim 11, the first phase finder configured to generate a first fractional phase signal of a four-phase variable clock (CKV) signal based on at least one of the four-phase CKV signal or a reference frequency (FREF) signal.

17. The phase locked loop (PLL) of claim 16, the four-phase CKV signal associated with at least one of:

a first clock signal and a first corresponding phase;

a second clock signal and a second corresponding phase;

a third clock signal and a third corresponding phase;

or

a fourth clock signal and a fourth corresponding phase.

18. The phase locked loop (PLL) of claim 17:

the first corresponding phase associated with at least about zero degrees;

the second corresponding phase associated with at least about ninety degrees;

the third corresponding phase associated with at least about one hundred and eighty degrees; and

the fourth corresponding phase associated with at least about two hundred and seventy degrees.

19. The phase locked loop (PLL) of claim 17, the second phase finder configured to cover at least about one fourth of a DCO period based on the four-phase CKV signal.

20. A method for locking a phase locked loop (PLL), comprising:

generating a first fractional phase signal of a multi-phase variable clock (CKV) signal based on at least one of the multi-phase CKV signal or a reference frequency (FREF) signal, the multi-phase CKV signal associated with one or more clock signals and one or more corresponding phases;

generating a second fractional phase signal of the multi-phase CKV signal based on at least one of the multi-phase CKV signal, a frequency command word (FCW) signal, or a phase reference (PHR) signal; and

selecting at least one of the first fractional phase signal or the second fractional phase signal based on a phase error (PHE) signal.