Scalable high performance 3D graphics

• US 8,593,468 B2
• Filed: 10/05/2010
• Issued: 11/26/2013
• Est. Priority Date: 03/22/2002
• Status: Expired due to Term

• Current Assignee: Gamehancement LLC (Jeffrey M. Gross)
• Original Assignee: Alandro Consulting NY LLC (Intellectual Ventures LLC)
• Inventors: Deering, Michael F., Lavelle, Michael G.
• Primary Examiner(s): Richer, Joni
• Application Number:
  US12/898,249
• Publication Number:
  US 20110221742A1
• Time in Patent Office: 1,148 Days
• Field of Search: 345501-506, 345/519, 345/520, 345/522, 345/530, 345/536, 345/541, 345/544, 345/545, 345/552, 345/581, 345/582, 709/251
• US Class Current: 345/520
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 5/70 Denoising; Smoothing

Abstract

A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Claims

1. A method, comprising:

storing one or more samples of an interleave of a super-sampled frame buffer in a memory of a node of a ring topology, the node dedicated to the interleave;

in response to receiving a graphics primitive loop packet at the node, executing a graphics rendering specified in the graphics primitive loop packet;

in response to receiving a draw pixel loop packet at the node, performing a conditional sample update function of the one or more samples in the interleave; and

in response to receiving a video pixel loop packet at the node, retrieving the one or more samples in the interleave stored in the memory and modifying the video pixel loop packet in accordance with the one or more samples to yield a modified video pixel loop packet.

2. The method of claim 1, wherein the executing the graphics rendering includes accessing a texture store in the memory of the node as required by the graphics primitive loop packet.

3. The method of claim 2, further comprising sending the modified video pixel loop packet to another node on the ring topology.

4. The method of claim 3, wherein the sending comprises:

in response to the node not being a last node in the ring topology, sending the modified video pixel loop packet to a neighboring node dedicated to a different interleave; and

in response to the node being the last node in the ring topology, sending the modified video pixel loop packet to a loop interface node for conversion into a video output signal.

5. The method of claim 3, further comprising:

receiving the modified video pixel loop packet as further modified by at least one other node in the ring topology; and

updating the texture store in the memory of the node in accordance with the modified video pixel loop packet as further modified by the at least one other node.

6. The method of claim 2, further comprising storing a rendered image in the texture store.

7. The method of claim 1, further comprising assigning the interleave to the node, including assigning the interleave to be non-redundant with respect to interleaves of the super-sampled frame buffer assigned to remaining nodes on the ring topology.

8. The method of claim 1, further comprising, in response to receiving the video pixel loop packet:

identifying a subset of the one or more samples within an active area of a currently defined antialiasing filter; and

applying the antialiasing filter to the subset of the one or more samples to yield a partial convolution result.

9. The method of claim 8, wherein the modifying the video pixel loop packet includes:

generating one or more convolution coefficients associated with a center point of the antialiasing filter and the subset of the one or more samples;

performing convolution of the subset of the one or more samples using the one or more coefficients; and

performing partial summation of a result of the convolution with one or more partial results contained in the video pixel loop packet.

10. The method of claim 1, wherein the executing the graphics rendering includes at least one of clip checking, clipping, vertex shading, scan converting, programmable shading on pixels, programmable shading on micropolygon vertices, texturing, surface tessellation, or displacement mapping.

11. The method of claim 1, further comprising receiving at least one of the graphics primitive loop packet, the draw pixel loop packet, or the video pixel loop packet over a point-to-point unidirectional link of the ring topology.

12. A tangible computer-readable storage device having stored thereon computer-executable instructions that, in response to execution, cause a computing system to perform operations, including:

maintaining one or more samples of an assigned interleave of a super-sampled frame buffer in a memory of a node of a loop architecture, wherein the node is dedicated to the assigned interleave;

performing a graphics rendering specified in a graphics primitive loop packet;

performing a condition sample update function of the one or more samples in the assigned interleave in accordance with a draw pixel loop packet; and

retrieving the one or more samples in the assigned interleave from the memory in response to receiving a video pixel loop packet, and modifying the video pixel loop packet based on the one or more samples to generate a modified video pixel loop packet.

13. The tangible computer-readable storage device of claim 12, wherein the performing the graphics rendering includes accessing a texture store in the local memory of the node in accordance with instructions in the graphics primitive loop packet.

14. The tangible computer-readable storage device of claim 13, the instructions further comprising sending the modified video loop packet to another node on the loop architecture.

15. The tangible computer-readable storage device of claim 14, the operations further including:

receiving the modified video pixel loop packet as further modified by at least one other node in the loop architecture; and

extracting texture data from the modified video pixel loop packet as further modified by the at least one other node for storage in the texture store.

16. The tangible computer-readable storage device of claim 12, the operations further including:

in response to receiving the video pixel loop packet;

determining a subset of the one or more samples that are within an active area of an antialiasing filter; and

applying the antialiasing filter to the subset of the one or more samples to yield a partial conversion result.

17. The tangible computer-readable storage device of claim 12, wherein the modifying the video pixel loop packet includes:

determining one or more convolution coefficients associated with a center point of the antialiasing filter and the subset of the one or more samples;

performing convolution of the subset of the one or more samples based on the one or more convolution coefficients; and

summing a result of the convolution with one or more partial results included in the video pixel loop packet.

18. The tangible computer-readable storage device of claim 12, wherein the performing the graphics rendering includes at least one of clip checking, clipping, vertex shading, scan converting, programmable shading on pixels, programmable shading on micropolygon vertices, texturing, surface tessellation, or displacement mapping.

19. A system comprising:

means for exchanging data with one or more nodes in a ring topology;

means for storing one or more samples of an interleave of a super-sampled frame buffer;

means for rendering a graphic specified in a graphics primitive loop packet;

means for performing a condition sample update function of the one or more samples in the interleave in accordance with a draw pixel loop packet;

means for retrieving the one or more samples in the interleave from the means for storing in response to receiving a video pixel loop packet; and

means for modifying the video pixel loop packet based on the one or more samples to generate a modified video pixel loop packet,

wherein the means for storing, the means for performing, the means for retrieving, and the means for modifying are dedicated to the interleave.

20. The system of claim 19, further comprising means for sending the modified video pixel loop packet to another node on the ring topology.

21. An apparatus comprising:

a loop interface configured to send and receive packets on a ring topology;

a memory configured to store one or more samples of an interleave of a super-sampled frame buffer, the memory dedicated to the interleave;

a render stage configured to receive a graphics primitive loop packet and to execute a graphics rendering specified in the graphics primitive loop packet, wherein the renders stage is dedicated to the interleave;

a sample fill stage configured to perform a conditional sample update function of the one or more samples in the interleave in response to receiving a draw pixel loop packet, the sample fill stage dedicated to the interleave; and

a video output stage configured to receive a video pixel loop packet, to retrieve the one or more samples in the interleave stored in the memory, and to modify the video pixel loop packet in accordance with the one or more samples to yield a modified video pixel loop packet,

wherein the render stage, the sample fill stage, and the video output stage are dedicated to the interleave.

22. The apparatus of claim 21, wherein the render stage is configured to access a texture store in the memory as required by the graphics primitive loop packet.

23. The apparatus of claim 22, wherein the loop interface is configured to send the modified video pixel loop packet to a node on the ring topology.

24. The apparatus of claim 23, wherein the loop interface is configured to receive the modified video pixel loop packet as further modified by the node on the ring topology, and the render stage is configured to update the texture store in the memory in accordance with the modified video pixel loop packet as further modified by the node.

25. The apparatus of claim 21, wherein, in response to receiving the video output stage, the video output stage is further configured to:

identify a subset of the one or more samples within an active area of a currently defined antialiasing filter; and

apply the antialiasing filter to the subset of the one or more samples to yield a partial convolution result.

26. The apparatus of claim 25, wherein the video output stage is further configured to:

generate one or more convolution coefficients associated with a center point of the antialiasing filter and the subset of the one or more samples;

perform convolution of the subset of the one or more samples using the one or more coefficients; and

perform partial summation of a result of the convolution with one or more partial results contained in the video pixel loop packet.

27. An apparatus, comprising:

a memory, associated with a node of a ring topology, configured to store one or more samples of an interleave of a super-sampled frame buffer, the memory dedicated to the interleave; and

a video output component configured to receive a video pixel loop packet, to retrieve the one or more samples in the interleave from the memory, and modify the video pixel loop packet in accordance with the one or more samples to yield a modified video pixel loop packet, wherein the video output stage is dedicated to the interleave.

28. The apparatus of claim 27, further comprising a render component configured to receive a graphics primitive loop packet and execute a graphics rendering specified in the graphics primitive loop packet, wherein the render component is dedicated to the interleave.

29. The apparatus of claim 27, further comprising a sample fill component configured to perform a conditional sample update function of the one or more samples in the interleave in response to reception of a draw pixel loop packet, wherein the sample fill component is dedicated to the interleave.

30. A method, comprising:

storing one or more samples of an interleave of a super-sampled frame buffer in a memory of a node of a ring topology, the node dedicated to the interleave; and

in response to receiving a video pixel loop packet at the node, retrieving the one or more samples of the interleave stored in the memory and modifying the video pixel loop packet in accordance with the one or more samples to yield a modified video pixel loop packet.

31. The method of claim 30, further comprising:

in response to receiving a graphics primitive loop packet at the node, executing a graphics rendering specified in the graphics primitive loop packet.

32. The method of claim 30, further comprising:

in response to receiving a draw pixel loop packet at the node, performing a conditional sample update function of the one or more samples of the interleave.