Semiconductor memory device

• US 8,593,868 B2
• Filed: 04/23/2012
• Issued: 11/26/2013
• Est. Priority Date: 04/21/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Park, Jin Su
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/453,440
• Publication Number:
  US 20120268996A1
• Time in Patent Office: 582 Days
• Field of Search: 365/185.12
• US Class Current: 365/185.12
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor memory device includes a memory cell array including memory block groups each coupled to bit lines, a page buffer group coupled to first bit lines of a first memory block group and configured to control voltages of the first bit lines of the first memory block group depending on data to be stored in memory cells in a program operation and configured to sense the voltage of the first bit lines in a read operation, at least one bit line coupling circuit configured to couple first bit lines of a n^th memory block group to the page buffer group by selectively coupling first bit lines of the first to n^th memory block groups in response to bit line coupling signals, and bit line control circuits configured to control second bit lines of the memory block groups in response to bit line control signals.

Claims

1. A semiconductor memory device, comprising:

a memory cell array comprising two or more memory block groups each coupled to bit lines;

a page buffer group coupled to first bit lines of a first memory block group and configured to control voltages of the first bit lines of the first memory block group depending on data to be stored in memory cells in a program operation and configured to sense the voltage of the first bit lines in a read operation;

at least one bit line coupling circuit configured to couple first bit lines of a n^th memory block group, selected from among the memory block groups, to the page buffer group by selectively coupling first bit lines of the first to n^th memory block groups in response to bit line coupling signals; and

bit line control circuits configured to control second bit lines of the memory block groups in response to bit line control signals.

2. The semiconductor memory device of claim 1, wherein in the program operation, the bit line control circuit of the n^th memory block group precharges the second bit lines of the n^th memory block group, and the bit line control circuits of the remaining memory block groups set the second bit lines of the remaining memory block groups in a floating state.

3. The semiconductor memory device of claim 1, wherein in the read operation, the bit line control circuit of the n^th memory block group discharges the second bit lines of the n^th memory block group, and the bit line control circuits of the remaining memory block groups precharge the second bit lines of the remaining memory block groups.

4. The semiconductor memory device of claim 1, further comprising a voltage supply circuit configured to supply voltages for the program operation or the read operation to a selected memory block of the n^th memory block group.

5. The semiconductor memory device of claim 1, wherein the bit line coupling circuits are configured to disconnect the second bit lines of the memory block groups when the first bit lines of the first to n^th memory block groups are connected to each other.

6. The semiconductor memory device of claim 1, wherein the bit line coupling circuit comprises:

even bit line coupling circuits configured to control a connection between even bit lines of the memory block groups in response to even bit line coupling signals of the bit line coupling signals; and

odd bit line coupling circuits configured to control a connection between odd bit lines of the memory block groups in response to odd bit line coupling signals of the bit line coupling signals.

7. The semiconductor memory device of claim 6, wherein, when the even bit lines of the n^th memory block group are selected as the first bit lines thereof, the even bit line coupling circuits couple the even bit lines of the n^th memory block group to the even bit lines of memory block groups disposed between the n^th memory block group and the page buffer group.

8. The semiconductor memory device of claim 7, wherein the odd bit line coupling circuits disconnect the odd bit lines of the memory block groups from each other.

9. The semiconductor memory device of claim 6, wherein, when the odd bit lines of the n^th memory block group are selected as the first bit lines thereof, the odd bit line coupling circuits couple the odd bit lines of the n^th memory block group to the odd bit lines of memory block groups disposed between the n^th memory block group and the page buffer group.

10. The semiconductor memory device of claim 9, wherein the even bit line coupling circuits disconnect the even bit lines of the memory block groups from each other.

11. The semiconductor memory device of claim 1, wherein the bit line control circuits are configured to set the second bit lines of the memory block groups in one of a precharge state, a discharge state, and a floating state.

12. The semiconductor memory device of claim 1, wherein the bit line control circuits are configured to set the second bit lines of the memory block groups in a precharge state or a floating state in the program operation and in the precharge state or a discharge state in the read operation, depending on whether the memory block groups are selected as the n^th memory block group.

13. The semiconductor memory device of claim 1, further comprising a controller configured to generate the bit line control signals and the bit line coupling signals in response to an address signal.

14. The semiconductor memory device of claim 1, wherein:

the page buffer group comprises page buffers corresponding to respective pairs of the first and second bit lines of the first memory block group, and

each of the page buffers comprises a bit line select circuit configured to select one bit line of the pair in response to a bit line select signal.

15. A semiconductor memory device, comprising:

two or more memory block groups each comprising memory strings coupled between a common source line and respective bit lines;

a page buffer group configured to control voltages of first bit lines of a memory block group, selected from among the memory block groups, depending on data to be stored in memory cells coupled to the first bit lines in a program operation and configured to sense the voltage of the first bit lines in a read operation;

at least one bit line coupling circuit configured to couple the first bit lines of the selected memory block group to the page buffer group in response to bit line coupling signals; and

two or more bit line control circuits configured to couple second bit lines of the selected memory block group to the common source line thereof and control voltages of second bit lines of memory blocks remaining among the memory block groups depending on the program operation and the read operation in response to the bit line control signals.

16. The semiconductor memory device of claim 15, wherein the bit line coupling circuit is configured to couple the first bit lines of the selected memory block group to the page buffer group by coupling first bit lines of memory block groups between the selected memory block group and the page buffer group.

17. The semiconductor memory device of claim 15, wherein the bit line coupling circuit is configured to couple the first bit lines of the selected memory block group to the page buffer group by coupling first bit lines of the memory block groups and disconnecting the second bit lines of the memory block groups.

18. The semiconductor memory device of claim 15, wherein the bit line coupling circuit comprises:

even bit line coupling circuits configured to control a connection between even bit lines the memory block groups in response to even bit line coupling signals of the bit line coupling signals; and

odd bit line coupling circuits configured to control a connection between odd bit lines of the memory block groups in response to odd bit line coupling signals of the bit line coupling signals.

19. The semiconductor memory device of claim 18, wherein, when the even bit lines of the selected memory block group are selected as the first bit lines thereof, the even bit line coupling circuits couple the even bit lines of the selected memory block group to the even bit lines of memory block groups disposed between the selected memory block group and the page buffer group.

20. The semiconductor memory device of claim 19, wherein the odd bit line coupling circuits disconnect the odd bit lines of the memory block groups from each other.

21. The semiconductor memory device of claim 18, wherein, when the odd bit lines of the selected memory block group are selected as the first bit lines thereof, the odd bit line coupling circuit couple the odd bit lines of the selected memory block group to the odd bit lines of memory block groups disposed between the selected memory block group and the page buffer group.

22. The semiconductor memory device of claim 21, wherein the even bit line coupling circuits disconnect the even bit lines of the memory block groups from each other.

23. The semiconductor memory device of claim 15, wherein the bit line control circuits are configured to set the second bit lines bit lines of the memory block groups in one of a precharge state, a discharge state, and a floating state.

24. The semiconductor memory device of claim 15, wherein the bit line control circuits are configured to set the second bit lines of the memory block groups in a precharge state or a floating state in the program operation and in the precharge state or a discharge state in the read operation, depending on whether the memory block groups are selected as the selected memory block group.

25. The semiconductor memory device of claim 15, wherein in the program operation, the bit line control circuit of the selected memory block group is configured to precharge the second bit lines of the selected memory block group by using voltage supplied to the common source line thereof, and the bit line control circuits of the remaining memory block groups are configured to set the voltages of the second bit lines of the remaining memory block groups in a floating state.

26. The semiconductor memory device of claim 15, wherein in the read operation, the bit line control circuit of the selected memory block group is configured to discharge the second bit lines of the selected memory block group through the common source line thereof, and the bit line control circuits of the remaining memory block groups are configured to precharge the voltages of the second bit lines of the remaining memory block groups.

27. The semiconductor memory device of claim 15, further comprising a voltage supply circuit configured to supply the common source lines of the memory block groups with a power supply voltage in the program operation and a ground voltage in the read operation.

28. The semiconductor memory device of claim 27, wherein the voltage supply circuit is configured to supply a program voltage and a program pass voltage for the program operation to a memory block, selected from among memory blocks of the selected memory block group, and a read voltage and a read pass voltage for the read operation to the selected memory block.

29. The semiconductor memory device of claim 15, further comprising a controller configured to generate the bit line control signals and the bit line coupling signals in response to an address signal.

30. The semiconductor memory device of claim 15, wherein:

the page buffer group comprises page buffers corresponding to respective pairs of the first and second bit lines of the selected memory block group, and

each of the page buffers comprises a bit line select circuit configured to select one bit line of the pair in response to a bit line select signal.