Apparatuses and methods including memory array and data line architecture

• US 8,593,869 B2
• Filed: 07/27/2011
• Issued: 11/26/2013
• Est. Priority Date: 07/27/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/192,248
• Publication Number:
  US 20130028023A1
• Time in Patent Office: 853 Days
• Field of Search: 365/130
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

Claims

1. A device comprising:

a first memory cell located in a first device level of the device;

a second memory cell coupled to the first memory cell and located in a second device leve the device;

at least a portion of a transistor located in a substrate of the device; and

a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell, wherein the transistor includes a first node coupled to the data line and a second node coupled to an additional data line, wherein the data line has a length in a first direction, and the additional data line has a length in the first direction, and wherein the additional data line is located between the data line and the transistor.

2. The device of claim 1, wherein the data line includes an array data line.

3. The device of claim 1, further comprising an additional transistor coupled to the data line, wherein the data line is located between the additional transistor and the first memory cell.

4. The device of claim 1, wherein the transistor is included in a multiplexer of the device.

5. The device of claim 1, wherein the transistor is configured to operate as a pass gate.

6. The device of claim 1, wherein the transistor is included in a select circuit of the device, and the select circuit is configured to couple the data line to an additional data line.

7. A device comprising:

a first memory cell located in a first device level of the device;

a second memory cell coupled to the first memory cell and located in a second device level of the device;

at least a portion of a transistor located in a substrate of the device; and

a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell; and

an additional data line coupled to the transistor, wherein the additional data line includes a local data line.

8. A device comprising

a first memory cell located in a first device level of the device;

a second memory cell coupled to the first memory cell and located in a second device level of the device;

at least a portion of a transistor located in a substrate of the device; and

a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell, wherein the transistor includes a first node coupled to the data line and a second node coupled to a conductive line, wherein the data line has a length in a first direction, and the conductive line has a length in a second direction.

9. The device of claim 8, wherein the conductive line includes a source line.

10. The device of claim 8, wherein the conductive line is located between the data line and the transistor.

11. A device comprising:

a first memory cell located in a first device level of the device;

a second memory cell coupled to the first memory cell and located in a second device level of the device;

at least a portion of a transistor located in a substrate of the device; and

a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell, wherein the transistor is included in a bias circuit of the device, and the bias circuit is configured to couple the data line to a reference voltage.

12. A device comprising:

a data line having a first side and a second side opposing the first side;

a first memory cell string coupled to the data line;

a second memory cell string coupled to the data line, wherein the first and second memory cell strings are located on the first side of the data line; and

a transistor coupled to the data line, wherein the transistor is located on the second side of the data line.

13. The device of claim 12, wherein the data line includes a first portion, a second portion, and a third portion, the third portion being between the first and second portion, the first memory cell string is coupled to the data line at the first portion, the second memory cell string is coupled to the data line at the second portion, and the transistor is coupled to the data line at the third portion.

14. The device of claim 12, further comprising an additional transistor coupled to the data line, wherein the additional transistor is located on the second side of the data line.

15. The device of claim 14, further comprising a sense circuit coupled to the transistor.

16. The device of claim 12, further comprising:

an additional data line having a length in a same direction as a length of the data line, the additional data line having a first side and a second side opposing the first side of the additional data line;

a third memory cell string coupled to the additional data line;

a fourth memory cell string coupled to the additional data line, wherein the third and fourth memory cell strings are located on the first side of the additional data line; and

an additional transistor coupled to the additional data line, wherein the additional transistor is located on the second side of the additional data line.

17. The device of claim 16, wherein the transistor and the additional transistor share a same node.

18. The device of claim 17, wherein the data line and the additional data line comprise array data lines, and further comprising a local data line coupled to the same node shared by the first and second transistors, wherein the local data line has a length in the same direction as the data line and the additional data line.

19. The device of claim 17, further comprising a source line coupled to the same node shared by the first and second transistors, wherein the source line has a length in a direction different from a direction of the direction of the lengths of the data and additional data lines.

20. A device comprising:

a circuit including at least a portion of a circuit located in a substrate;

a first data line overlying the portion of the circuit;

a second data line overlying the portion of the circuit;

a first memory cell string coupled to the first data line and overlying the first data line; and

a second memory cell string coupled to the second data line and overlying the second data line, wherein the circuit is configured to selectively couple at least one of the first and second data lines to a node.

21. The device of claim 20, wherein the circuit is configured to selectively couple one of the first and second data lines to a sense circuit.

22. The device of claim 20, wherein the circuit is configured to selectively couple one of the first and second data lines to a source line.

23. The device of claim 20, wherein the circuit includes a transistor coupled between the first data line and the node.

24. The device of claim 23, wherein the circuit includes an additional transistor coupled between the second data line and the node.

25. The device of claim 23, further comprising a conductive line coupled to the node, wherein the first data line has length in a first direction, and the conductive line has a length in a second direction.

26. The device of claim 23, further comprising an additional data line coupled to the node, wherein the first data line has length in a first direction, and the additional data line has a length in the first direction.

27. The device of claim 23, wherein the circuit includes a first transistor coupled between the first data line and the node, a second transistor coupled between the second data line and the node, a third transistor coupled between the first data line and an additional node, and a fourth transistor coupled between the second data line and the additional node.

28. The device of claim 23, wherein the circuit is configured to selectively couple at least one of the first and second data lines to an additional node, and the circuit includes a first transistor coupled between the first data line and the node, and a second transistor coupled between the second data line and the additional node.

29. The device of claim 23, wherein the substrate includes a first region and a second region located in the first region, and the circuit includes a source region and a drain region located in the second region, and the first region and the source and drain regions include material of a same conductivity type.

30. The device of claim 23, further comprising a first device level, a second device level, and a local data line located in the first device level, wherein the first and second data lines are located in the second device level.

31. The device of claim 30, further comprising a global data line located in the second device level and coupled to the local data line.

32. The device of claim 30, further comprising a third device level and a global data line located in the third device level and coupled to the local data line.

33. A device comprising:

a first device level, a second device level, and a third device level, the second device level being between the first and third device levels;

a memory cell string having at least one memory cell located between the second and third device levels;

a data line coupled to the memory cell string, the data line located in the second device level;

a first additional data line located in the first device level;

a second additional data line coupled to the first additional data line, the second additional data line located in the third device level; and

a circuit configured to provide information from the data line to at least one of the first the additional data line and the second additional data line.

34. The device of claim 33, wherein the data line includes an array data line.

35. The device of claim 33, wherein the first additional data line includes a local data line.

36. The device of claim 33, wherein the second additional data line includes a global data line.

37. The device of claim 33, further comprising a first memory array and a second memory array, a third additional data line coupled to the second additional data line, and an additional circuit, wherein the memory cell string is located in the first memory array, the second memory array includes an additional memory cell string, and the additional circuit is configured to provide information from the additional memory cell string to the third additional data line.

38. The device of claim 37, further comprising a first conductive line coupled between the first and second additional data lines, and a second conductive line coupled between the second and third additional data lines, wherein the first conductive line has a length in a first direction, and the second conductive line has a length in the first direction.

39. The device of claim 33, further comprising a sense circuit coupled to the first and second additional data lines.

40. The device of claim 33, further comprising a conductive line having a length in a first direction, and a transistor coupled between the conductive line and the second additional data line, wherein the second additional data line has a length in a second direction.

41. The device of claim 33, further comprising a first memory array, a second memory array, and a third additional data line, wherein the first additional data line includes a first local data line, the second additional data line includes a global data line, and the third additional data includes a second local data line coupled to the global data line.

42. The device of claim 41, further comprising a select circuit configured to couple the global data line to a sense circuit.

43. The device of claim 41, further comprising a bias circuit configured to couple the global data line to a source line.

44. The device of claim 41, further comprising a sense circuit coupled to the global data line.

45. A method comprising:

forming at least a portion of a transistor in a substrate;

forming a data line coupled to the transistor; and

forming memory cells coupled to the data line wherein forming the memory cells includes forming a first memory cell in a first device level of a device and forming a second memory cell in a second device level of the device, and the first and second memory cells are formed after the data line is formed, wherein forming the data line includes forming a conductive line coupled to the transistor before forming the data line, and forming the data line directly contacting the conductive line.

46. A method comprising:

forming at least a portion of a transistor in a substrate;

forming a data line coupled to the transistor;

forming memory cells coupled to the data line, wherein forming the memory cells includes forming a first memory cell in a first device level of a device and forming a second memory cell in a second device level of the device, and the first and second memory cells are formed after the data line is formed; and

forming an additional data line coupled to the transistor before forming the data line.

47. The method of claim 46, wherein forming the additional data line includes forming a conductive line coupled to the transistor, and forming the additional data line coupled to the conductive line.

48. A method comprising:

forming at least a portion of a transistor in a substrate;

forming a data line coupled to the transistor;

forming memory cells coupled to the data line, wherein forming the memory cells includes forming a first memory cell in a first device level of a device and forming a second memory cell in a second device level of the device, and the first and second memory cells are formed after the data line is formed;

forming an additional transistor before forming the data line; and

forming a conductive line coupled to the additional transistor before forming the data line, wherein the conductive line and the data line are formed such that the conductive line has a length in a first direction and the data line has a length in a second direction.