Apparatuses and methods including memory array and data line architecture
First Claim
Patent Images
1. A device comprising:
- a first memory cell located in a first device level of the device;
a second memory cell coupled to the first memory cell and located in a second device leve the device;
at least a portion of a transistor located in a substrate of the device; and
a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell, wherein the transistor includes a first node coupled to the data line and a second node coupled to an additional data line, wherein the data line has a length in a first direction, and the additional data line has a length in the first direction, and wherein the additional data line is located between the data line and the transistor.
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Abstract
Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.
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Citations
48 Claims
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1. A device comprising:
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a first memory cell located in a first device level of the device; a second memory cell coupled to the first memory cell and located in a second device leve the device; at least a portion of a transistor located in a substrate of the device; and a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell, wherein the transistor includes a first node coupled to the data line and a second node coupled to an additional data line, wherein the data line has a length in a first direction, and the additional data line has a length in the first direction, and wherein the additional data line is located between the data line and the transistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A device comprising:
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a first memory cell located in a first device level of the device; a second memory cell coupled to the first memory cell and located in a second device level of the device; at least a portion of a transistor located in a substrate of the device; and a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell; and an additional data line coupled to the transistor, wherein the additional data line includes a local data line.
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8. A device comprising
a first memory cell located in a first device level of the device; -
a second memory cell coupled to the first memory cell and located in a second device level of the device; at least a portion of a transistor located in a substrate of the device; and a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell, wherein the transistor includes a first node coupled to the data line and a second node coupled to a conductive line, wherein the data line has a length in a first direction, and the conductive line has a length in a second direction. - View Dependent Claims (9, 10)
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11. A device comprising:
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a first memory cell located in a first device level of the device; a second memory cell coupled to the first memory cell and located in a second device level of the device; at least a portion of a transistor located in a substrate of the device; and a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell, wherein the transistor is included in a bias circuit of the device, and the bias circuit is configured to couple the data line to a reference voltage.
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12. A device comprising:
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a data line having a first side and a second side opposing the first side; a first memory cell string coupled to the data line; a second memory cell string coupled to the data line, wherein the first and second memory cell strings are located on the first side of the data line; and a transistor coupled to the data line, wherein the transistor is located on the second side of the data line. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A device comprising:
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a circuit including at least a portion of a circuit located in a substrate; a first data line overlying the portion of the circuit; a second data line overlying the portion of the circuit; a first memory cell string coupled to the first data line and overlying the first data line; and a second memory cell string coupled to the second data line and overlying the second data line, wherein the circuit is configured to selectively couple at least one of the first and second data lines to a node. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A device comprising:
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a first device level, a second device level, and a third device level, the second device level being between the first and third device levels; a memory cell string having at least one memory cell located between the second and third device levels; a data line coupled to the memory cell string, the data line located in the second device level; a first additional data line located in the first device level; a second additional data line coupled to the first additional data line, the second additional data line located in the third device level; and a circuit configured to provide information from the data line to at least one of the first the additional data line and the second additional data line. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A method comprising:
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forming at least a portion of a transistor in a substrate; forming a data line coupled to the transistor; and forming memory cells coupled to the data line wherein forming the memory cells includes forming a first memory cell in a first device level of a device and forming a second memory cell in a second device level of the device, and the first and second memory cells are formed after the data line is formed, wherein forming the data line includes forming a conductive line coupled to the transistor before forming the data line, and forming the data line directly contacting the conductive line.
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46. A method comprising:
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forming at least a portion of a transistor in a substrate; forming a data line coupled to the transistor; forming memory cells coupled to the data line, wherein forming the memory cells includes forming a first memory cell in a first device level of a device and forming a second memory cell in a second device level of the device, and the first and second memory cells are formed after the data line is formed; and forming an additional data line coupled to the transistor before forming the data line. - View Dependent Claims (47)
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48. A method comprising:
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forming at least a portion of a transistor in a substrate; forming a data line coupled to the transistor; forming memory cells coupled to the data line, wherein forming the memory cells includes forming a first memory cell in a first device level of a device and forming a second memory cell in a second device level of the device, and the first and second memory cells are formed after the data line is formed; forming an additional transistor before forming the data line; and forming a conductive line coupled to the additional transistor before forming the data line, wherein the conductive line and the data line are formed such that the conductive line has a length in a first direction and the data line has a length in a second direction.
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Specification