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Apparatuses and methods including memory array and data line architecture

  • US 8,593,869 B2
  • Filed: 07/27/2011
  • Issued: 11/26/2013
  • Est. Priority Date: 07/27/2011
  • Status: Active Grant
First Claim
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1. A device comprising:

  • a first memory cell located in a first device level of the device;

    a second memory cell coupled to the first memory cell and located in a second device leve the device;

    at least a portion of a transistor located in a substrate of the device; and

    a data line coupled to the transistor and to the first memory cell, wherein the data line is located between the transistor and the first memory cell, wherein the transistor includes a first node coupled to the data line and a second node coupled to an additional data line, wherein the data line has a length in a first direction, and the additional data line has a length in the first direction, and wherein the additional data line is located between the data line and the transistor.

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