Clock masking scheme in a mixed-signal system
First Claim
1. A method in a mixed-signal system to prevent overlapping of clock edges of one or more digital clock signals and clock edges of one or more analog clock signals, the digital clock signals and the analog clock signals being digitally controlled, the method comprising:
- generating one or more timing window pulses that are centered around the clock edges of one of the digital clock signals or the analog clock signals;
combining the timing window pulses to generate a gating signal, the gating signal having an active logical level at each of the timing window pulses; and
applying the gating signal to gate or delay clock edges of the other one of the digital clock signals or the analog clock signals.
1 Assignment
0 Petitions
Accused Products
Abstract
A method in a mixed-signal system to prevent overlapping of clock edges of one or more digital clock signals and clock edges of one or more analog clock signals where the digital clock signals and the analog clock signals are digitally controlled includes generating one or more timing window pulses that are centered around the clock edges of one of the digital clock signals or the analog clock signals; combining the timing window pulses to generate a gating signal, the gating signal having an active logical level at each of the timing window pulses; and applying the gating signal to gate or delay clock edges of the other one of the digital clock signals or the analog clock signals.
41 Citations
8 Claims
-
1. A method in a mixed-signal system to prevent overlapping of clock edges of one or more digital clock signals and clock edges of one or more analog clock signals, the digital clock signals and the analog clock signals being digitally controlled, the method comprising:
-
generating one or more timing window pulses that are centered around the clock edges of one of the digital clock signals or the analog clock signals; combining the timing window pulses to generate a gating signal, the gating signal having an active logical level at each of the timing window pulses; and applying the gating signal to gate or delay clock edges of the other one of the digital clock signals or the analog clock signals. - View Dependent Claims (2, 3, 4)
-
-
5. A clock masking circuit in a mixed-signal system to prevent overlapping of clock edges of one or more digital clock signals and clock edges of one or more analog clock signals, the digital clock signals and the analog clock signals being digitally controlled, the clock masking circuit comprising:
-
one or more timing window generators configured to generate one or more timing window pulses that are centered around the clock edges of one of the digital clock signals or the analog clock signals; a combiner configured to combine the timing window pulses to generate a gating signal, the gating signal having an active logical level at each of the timing window pulses; and one or more latch circuits configured to apply the gating signal to gate or delay clock edges of the other one of the digital clock signals or the analog clock signals. - View Dependent Claims (6, 7, 8)
-
Specification