Apparatus and method thereof for clock and data recovery of N-PAM encoded signals using a conventional 2-PAM CDR circuit
First Claim
1. An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit, comprising:
- a number of N−
1 comparators for comparing an input data stream to N−
1 configurable thresholds, wherein the input data stream is N-PAM modulated and the N−
1 configurable thresholds are N−
1 different voltage levels;
a number of N−
1 of edge detectors respectively connected to the N−
1 comparators for detecting transitions from one logic value to another logic value, wherein N is a discrete number greater than two;
a determination unit for determining if a detected transition is any one of a major transition and a minor transition, wherein a major transition is a logic value change in a most significant bit (MSB) and a least significant bit (LSB) remains at a low-logic value, and a minor transition is a logic value change in a LSB or a logic value change in the MSB and the LSB remains at a high-logic value, wherein the MSB and LSB are two bits out of 2 bits in the input data stream; and
asserting a transition signal if only a major transition or a minor transition has occurred, wherein the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream by phase aligning to the transitions in the input data stream.
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Accused Products
Abstract
An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit. The circuit comprises a number of N−1 comparators for comparing an input data stream to N−1 configurable thresholds, the input data stream is N-PAM modulated and the N−1 configurable thresholds are N−1 different voltage levels; a number of N−1 of edge detectors respectively connected to the N−1 comparators for detecting transitions from one logic value to another logic value, N is a discrete number greater than two; and a determination unit for determining if the detected transitions is any one of a major transition and a minor transition and asserting a transition signal if only a major transition or a minor transition has occurred, the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream.
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Citations
23 Claims
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1. An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit, comprising:
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a number of N−
1 comparators for comparing an input data stream to N−
1 configurable thresholds, wherein the input data stream is N-PAM modulated and the N−
1 configurable thresholds are N−
1 different voltage levels;a number of N−
1 of edge detectors respectively connected to the N−
1 comparators for detecting transitions from one logic value to another logic value, wherein N is a discrete number greater than two;a determination unit for determining if a detected transition is any one of a major transition and a minor transition, wherein a major transition is a logic value change in a most significant bit (MSB) and a least significant bit (LSB) remains at a low-logic value, and a minor transition is a logic value change in a LSB or a logic value change in the MSB and the LSB remains at a high-logic value, wherein the MSB and LSB are two bits out of 2 bits in the input data stream; and asserting a transition signal if only a major transition or a minor transition has occurred, wherein the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream by phase aligning to the transitions in the input data stream. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A receiver connected to a serial multimedia interface for processing high-speed multimedia signals transmitted by a transmitter over the serial multimedia interface, comprising:
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an adaptive equalizer for receiving an input data stream over the serial multimedia interface and generating an equalized input data stream, wherein the input data stream is a N-level pulse amplitude modulation (N-PAM) modulated data stream; an interface circuit connected to the adaptive equalizer for generating a transition signal indicating only major and minor transitions in the equalized input data stream and generating bit-data streams from the equalized input data stream, wherein N is a discrete number greater than two and the number of bit-data streams is based on the number of voltage levels in the input modulated data stream; a 2-PAM clock and data recover (CDR) circuit for locking on a signal used in transmission of the input data stream by phase aligning to the transitions in the input data stream based, in part, on the transition signal; and a data sampler for sampling the bit-data stream and generating serial bit streams, each of the serial bit streams includes k bits, wherein a major transition is a logic value change in a most significant bit (MSB) and a least significant bit (LSB) remains at a low-logic value, and a minor transition is a logic value change in a LSB or a logic value change in the MSB and the LSB remains at a high-logic value, wherein the MSB and LSB are two bits out of 2 bits in the input data stream. - View Dependent Claims (14, 15, 16, 17)
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18. A method for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit comprising:
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comparing an input data stream to N−
1 configurable thresholds, wherein the input data stream is N-PAM modulated and the N−
1 configurable thresholds are N−
1 different voltage levels;detecting transitions from one logic value to another logic value based on comparisons of the input data stream to the N−
1 configurable thresholds, wherein N is a discrete number greater than two; and
determining if the detected transitions include any one of a major transition and a minor transition; andasserting a transition signal if only a major transition or a minor transition has occurred, wherein the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream by phase aligning to the transitions in the input data stream based, in part, on the transition signal, wherein a major transition is a logic value change in a most significant bit (MSB) and a least significant bit (LSB) remains at a low-logic value, and a minor transition is a logic value change in a LSB or a logic value change in the MSB and the LSB remains at a high-logic value, wherein the MSB and LSB are two bits out of 2 bits in the input data stream. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification