Flash memory architecture with separate storage of overhead and user data

• US 8,595,421 B2
• Filed: 03/28/2012
• Issued: 11/26/2013
• Est. Priority Date: 08/25/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Estakhri, Petro, Nemazie, Siamack
• Primary Examiner(s): Tran, Denise
• Application Number:
  US13/432,763
• Publication Number:
  US 20120185754A1
• Time in Patent Office: 608 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data that comprises ECC data that is used for error checking with respect to the user data in the dedicated data blocks. The dedicated data blocks can be erased without erasing the ECC data that is used for error checking with respect to the user data in the dedicated data blocks.

Claims

1. A memory device, comprising:

a plurality of dedicated data blocks for storing user data; and

a plurality of dedicated overhead blocks for storing only overhead data that comprises ECC data that is used for error checking with respect to the user data in the dedicated data blocks;

wherein the dedicated data blocks are erasable without erasing the ECC data that is used for error checking with respect to the user data in the dedicated data blocks; and

wherein a dedicated overhead block comprises a plurality of overhead segments, wherein the overhead segments comprise physical block address registers configured to store physical block addresses defining respective dedicated data blocks.

2. The memory device of claim 1, wherein the plurality of overhead segments are located in a page of one or more pages of the dedicated overhead block.

3. The memory device of claim 2, wherein each dedicated data block comprises one or more pages.

4. The memory device of claim 3, wherein a single parity bit of error correction data is used for each page of user data.

5. The memory device of claim 2, further comprising a space manager that is configured to address only the overhead data.

6. The memory device of claim 5, wherein the space manager defines both the page in which the plurality of overhead segments are located and a segment offset within that page.

7. The memory device of claim 5, wherein the space manager defines the page in which the plurality of overhead segments are located.

8. The memory device of claim 5, wherein the space manager comprises status flags associated with the dedicated overhead block that comprises the plurality of overhead segments, the status flags defining the status of the dedicated overhead block that comprises the plurality of overhead segments.

9. The memory device of claim 1, wherein the memory device is configured to define the overhead segments of the plurality of overhead segments as available or current overhead segments, wherein an available overhead segment is an overhead segment that is unused, non-defective, and not obsolete and a current overhead segment is an overhead segment that is used, non-defective, and not obsolete.

10. The memory device of claim 1, wherein each overhead segment of the plurality of overhead segments supports an amount of user data stored in a single dedicated data block.

11. The memory device of claim 1, wherein each overhead segment of the plurality of overhead segments comprises flags for defining the status of user data and the status of a dedicated data block identified by that overhead segment.

12. The memory device of claim 1, wherein the dedicated overhead block that comprises the plurality of overhead segments comprises first and second overhead data fields.

13. The memory device of claim 12, wherein less than one half of the dedicated overhead block that comprises the plurality of overhead segments is reserved as the first overhead field.

14. The memory device of claim 1, wherein the overhead segments are further configured to store the ECC data that is used for error checking with respect to the user data in the dedicated data blocks, wherein each overhead segment stores ECC data that is used for error checking with respect to the user data in a respective one of the dedicated data blocks.

15. The memory device of claim 1, further comprising a space manager that is configured to store locations of the overhead segments such that the space manager respectively correlates virtual logical block addresses assigned to the user data in the respective dedicated data blocks by a host to the stored locations of the overhead segments.

16. A memory device, comprising:

a plurality of dedicated data blocks for storing user data; and

a plurality of dedicated overhead blocks for storing only overhead data that comprises ECC data that is used for error checking with respect to the user data in the dedicated data blocks;

wherein the dedicated data blocks are erasable without erasing the ECC data that is used for error checking with respect to the user data in the dedicated data blocks;

wherein each dedicated overhead block comprises one or more pages, each page comprising a plurality of overhead segments; and

wherein the memory device is configured to determine that a dedicated overhead block is full in response to determining that only one page of the dedicated data block is full.

17. The memory device of claim 16, wherein a page of a dedicated overhead block is full when all of the overhead segments in that page are obsolete, except for a last segment of that page that is used, non-defective, and non-obsolete.

18. The memory device of claim 16, wherein the memory device is configured to move overhead segments that are used, non-defective, and non-obsolete from a dedicated overhead block that is full to another dedicated overhead block.

19. A memory device, comprising:

a plurality of dedicated data blocks for storing user data; and

a plurality of dedicated overhead blocks for storing only overhead data that supports the user data in the plurality of dedicated data blocks;

wherein each dedicated overhead block comprises one or more pages, each page comprising a plurality of overhead segments;

wherein each dedicated data block comprises one or more pages; and

wherein the memory device is configured to store a range of virtual logical block addresses associated with a dedicated data block in an extension at an end of a page of the dedicated data block.

20. The memory device of claim 19, wherein the overhead data comprises ECC data that is used for error checking with respect to the user data in the dedicated data blocks.

21. The memory device of claim 19, wherein each overhead segment is configured to store overhead data supporting an amount of user data stored in a respective single dedicated overhead block of the plurality of dedicated data blocks.

22. The memory device of claim 21, wherein overhead data stored in each overhead segment and supporting an amount of user data stored in a respective single dedicated overhead block of the plurality of dedicated data blocks comprises ECC data that is used for error checking with respect to the user data in the respective single dedicated overhead block of the plurality of dedicated data blocks.

23. The memory device of claim 22, wherein the respective single dedicated overhead block of the plurality of dedicated data blocks is erasable without erasing the ECC data that is used for error checking with respect to the user data in the respective single dedicated overhead block of the plurality of dedicated data blocks.

24. The memory device of claim 21, wherein each overhead segment that is configured to store overhead data supporting an amount of user data stored in a respective single dedicated overhead block of the plurality of dedicated data blocks comprises a physical block address register configured to store a physical block address defining the respective single dedicated overhead block of the plurality of dedicated data blocks.