Micro-threaded memory

• US 8,595,459 B2
• Filed: 11/29/2004
• Issued: 11/26/2013
• Est. Priority Date: 11/29/2004
• Status: Active Grant

• Current Assignee: K.Mizra LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Hampel, Craig E., Richardson, Wayne S., Bellows, Chad A., Lai, Lawrence
• Primary Examiner(s): Chace, Christian P
• Assistant Examiner(s): Cygiel, Gary W
• Application Number:
  US10/998,402
• Publication Number:
  US 20060117155A1
• Time in Patent Office: 3,284 Days
• Field of Search: 711/167
• US Class Current: 711/168
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Claims

1. A synchronous memory device, comprising:

first and second bank groups, each comprising at least one storage array;

a request interface to receive first and second memory access read commands directed respectively to the first and second bank groups;

data path circuitry to output data from the first and second bank groups to at least one shared line of an external signalling path;

where a minimum time interval comprising a minimum number of clock cycles must elapse between successive read accesses to an open row of storage cells in a selected one of the storage arrays;

where the data path circuitry is to output, for an open first row in a first bank group storage array and a concurrently-open second row in a second bank group storage array and during respective portions of a first time interval, first data from the first bank group storage array, responsive to the first memory access read command, and second data from the second bank group storage array, responsive to the second memory access read command, to the at least one shared line of the external signalling path; and

where the first time interval is less than twice the minimum time interval.

2. The memory device of claim 1, where:

one or more bitlines couple the first bank group storage array with the at least one shared line of the external signalling path;

one or more bitlines couple the second bank group storage array with the at least one shared line of the external signalling path;

the memory device further comprises a buffer operatively coupling the second bank group storage array with the at least one shared line of the external signalling path, but not operatively coupling the first bank group storage array with the at least one shared line of the external signalling path, the buffer being used to delay the output of the second data relative to the first data.

3. The memory device of claim 2, where the first data and the second data are retrieved from the respective first and second bank group storage arrays, where the retrieval of the first data from the first bank group storage array and retrieval of the second data from the second bank group storage array overlap at least partially in time, and where the buffer is to delay the output of the second data onto the at least one shared line of the external signalling path to a time mutually exclusive from the output of the first data onto the at least one shared line of the external signalling path.

4. The memory device of claim 2, where the data path circuitry further comprises a bank multiplexer to output the first data and the second data to the at least one shared line of the external signalling path, where the bank multiplexer is coupled to each of the first and second bank group storage arrays via respective sets of the one or more respective bitlines, and where the bank multiplexer is to couple the respective set for the first bank group storage array to the at least one shared line of the external signalling path and the respective set for the second bank group storage array to the at least one shared line of the external signalling path at mutually-exclusive times.

5. The memory device of claim 1, where each storage array comprises at least two subbanks of memory cells, where the request interface receives two column addresses in association with a single memory access read command and directs each of the two column addresses to an open row in respective ones of the subbanks, and where data retrieved from each of the respective subbanks is to be output on mutually-exclusive signalling lines of the external signalling path.

6. The memory device of claim 1, where each storage array comprises an array of dynamic random access memory cells.

7. The memory device of claim 1, where the data path circuitry further comprises at least one data serializer to couple sets of one or more bitlines for each of the first one and the second one of the bank groups to the at least one shared line of the external signalling path, and where each line of the at least one shared line has a higher data rate than any one of the respective bitlines.

8. The memory device of claim 1, where the memory device is to output first data, second data, third data and fourth data from respective first and second bank group storage arrays during the first time interval, the first data and second data to be output in time-multiplexed manner on a first set of at least one shared line of the external signalling path, the third data and the fourth data to be output in time-multiplexed manner on a second set of at least one shared line of the external signalling path, the first and second sets being mutually-exclusive, where the first and third data correspond to the first memory access read command but respective column addresses in respective subbanks of the first bank group, where the second and the fourth data correspond to the second memory access command but respective column addresses in respective subbanks of the second bank group.

9. The memory device of claim 1, where the first time interval is less than or equal to the minimum time interval.

10. The memory device of claim 1, where the memory device further comprises at least one bank multiplexer to receive the first data from the first bank group storage array and the second data from the second bank group storage array, and to switch each of the first and second data in sequence to at least one shared line of the external signaling path during the respective portions of the time interval, each respective portion less than the minimum time interval.

11. In a synchronous memory device having first and second bank groups, each comprising at least one storage array, and for which a minimum time interval comprising a minimum number of clock cycles must elapse between initiation of a column access operation for read data in an open row within one of the arrays and initiation of another column access operation for read data in the open row, a method comprising:

receiving first and second memory access read commands directed respectively to concurrently-open rows in the first and second bank groups, at a request interface;

retrieving, in a first column access operation responsive to the first memory access read command, first data from a first one of the storage arrays in the first bank group;

retrieving, in a second column access operation responsive to the second memory access read command, second data from a second one of the storage arrays in the second bank group; and

outputting the first data and the second data from the memory device onto at least one shared line of an external signalling path during respective portions of a first time interval, wherein the first time interval is less than twice the minimum time interval.

12. The method of claim 11, further comprising using at least one bank multiplexer to output the first data and the second data to the at least one shared line of the external signalling path.

13. The method of claim 12, where each bank multiplexer of the at least one bank multiplexer is bidirectional, and the method further comprises using at least one bank multiplexer to route data to one of the bank group storage arrays during a memory write request.

14. The method of claim 11, where each of the bank group storage arrays includes at least two subbanks of memory cells, and where the method further comprises receiving two column addresses in a single memory access read command, directing each of the two column addresses to respective subbanks of a bank group storage array, and outputting data retrieved from each of the respective sub-banks on mutually-exclusive sets of one or more signalling lines of the external signalling path.

15. The method of claim 11, further comprising using at least one data serializer to couple respective bitlines for each of the respective bank groups to the at least one shared line of the external signalling path, and where each line of the at least one shared line of the external signalling path has a higher data rate than any one of the respective bitlines.

16. The method of claim 11, where the first time interval is less than or equal to the minimum time interval.

17. The method of claim 11, where the method further comprises sequentially receiving at the request interface a row access command for the first one of the storage arrays, a row access command for the second one of the storage arrays, the first memory access read command, and the second memory access read command.

18. The method of claim 11, where the method further comprises:

sequentially receiving at the request interface a row access command for the first one of the storage arrays, a row access command for the second one of the storage arrays, the first memory access read command, the second memory access read command, a third memory access read command, and a fourth memory access read command;

retrieving, in a third column access operation responsive to the third memory address read command, third data from a third one of the storage arrays;

retrieving, in a fourth column access operation responsive to the fourth memory access read command, fourth data from a fourth one of the storage arrays; and

outputting the first and second data from the memory device onto at least one shared line of the external signalling path in a time interval less than twice the minimum time interval, and outputting the third and fourth data from the memory device onto at least one shared line of the external signaling path, in a time interval less than twice the minimum time interval.

19. The method of claim 18, where the outputting the first, second, third and fourth data is performed in a time interval less than twice the minimum time interval.

20. A synchronous memory device, comprising:

plural bank groups, each comprising at least one storage array;

a request interface to receive memory access read commands;

data path circuitry to output data from the plural bank groups to at least one shared line of an external signalling path;

where in any given one of the plurality of storage arrays, a minimum time interval comprising a number of clock cycles must elapse between initiation of a column access operation for read data to an open row in the given storage array and initiation of another column access operation for read data within the open row; and

where the memory device is to output onto the at least one shared line of the external signaling path, during respective subsets of a time interval less than twice the minimum time interval, first and second data from different concurrently-open rows in different ones of the bank groups, responsive to respective first and second memory access read commands received at the request interface.

21. The memory device of claim 20, where the time interval is less than or equal to the minimum time interval.

22. The memory device of claim 20, where the memory device further comprises at least one bank multiplexer to receive the first data from a first one of the bank groups and the second data from a second one of the bank groups, and to switch each of the first and second data in sequence to the at least one shared line of the external signaling path during the respective subsets of the time interval, each respective subset less than the minimum time interval.

23. A synchronous memory device, comprising:

plural bank groups, each comprising at least one storage array;

a request interface operable to receive memory access read commands;

data path circuitry operable to output data from the plural bank groups to at least one shared line of an external signalling path;

where

in any given one of the storage arrays, a minimum time interval comprising a number of clock cycles must elapse between initiation of a column access operation for read data to an open row in the given storage array and initiation of another column access operation for read data within the open row,

the memory device is operable to receive at the request interface a first row access command for a first one of the bank groups, a second row access command for a second one of the bank groups, a first memory access read command containing a first column address corresponding to the first row access command, and a second memory access read command containing a second column address corresponding to the second row access command, the second row being concurrently-open with the first row, and

the memory device is operable to output onto the at least one shared line of the external signaling path, and within respective subsets of a time interval less than twice the minimum time interval, first and second data respectively responsive to first and second memory access read commands.

24. The memory device of claim 23, where the memory device further comprises a bank multiplexer, a first buffer coupling the first one of the bank groups with the bank multiplexer and a second buffer coupling the second one of the bank groups with the bank multiplexer, where the bank multiplexer is operable to receive the first data from the first one of the bank groups and the second data from the second one of the bank groups, and to switch each of the first and second data in sequence to the at least one shared line of the external signaling path during the respective subsets of the time interval, each respective subset less than the minimum time interval, and where the first and second buffers are operable to delay the first and second data, respectively, such that notwithstanding relative time of receipt at the memory device of the first and second memory access read commands, the respective first and second data are output by the bank multiplexer at mutually-exclusive times.

25. The memory device of claim 23, where the storage arrays each comprise at least two subbanks of memory cells, where the request interface is operable to receive two column addresses in association with each of the first and second memory access read commands and to concurrently direct each of the two column addresses to respective subbanks of a storage array, and where the memory device is operable to concurrently output data responsively retrieved from each of the respective subbanks on mutually-exclusive signalling lines of the external signalling path.

26. The memory device of claim 23, where the memory device is operable to successively receive at the request interface the first row access command, the second row access command, the first memory access read command, and the second memory access read command.