Automatic internal trimming calibration method to compensate process variation

• US 8,595,544 B2
• Filed: 01/30/2013
• Issued: 11/26/2013
• Est. Priority Date: 06/17/2009
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hu, Chih-Ting, Chen, Ken-Hui, Hung, Chun-Hsiung
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US13/753,943
• Publication Number:
  US 20130145201A1
• Time in Patent Office: 300 Days
• Field of Search: 713/503
• US Class Current: 713/503
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target range after applying predefined reference cycles.

Claims

1. An integrated circuit having an automatic timing trimming capability, comprising:

an interface control block that receives a chip select signal, an external reference signal, and an automatic trimming enable signal and generates an internal chip control signal and an internal reference signal according to the external reference signal;

an internal timing circuit and a read fuse information block, the internal timing circuit being adapted to receive fuse information from the read fuse information block and generate a read-speed timing reference signal according to the fuse information and the internal chip control signal; and

a timing result combination and classification die corner circuit that receives the read-speed timing reference signal and the internal reference signal and generates a plurality of samples of the external reference signal according to the read-speed timing reference signal.

2. The integrated circuit as set forth in claim 1, wherein the read fuse information block is adapted to receive the fuse information from a fuse information memory block.

3. The integrated circuit as set forth in claim 2, further comprising an auto internal timing trimming circuit adapted to receive the plurality of samples of the reference signal, generate a classification of the plurality of samples, and generate a plurality of parameters adapted to adjust the internal timing circuit according to the classification.

4. The integrated circuit as set forth in claim 3, wherein the classification is one of a group consisting of a first classification, a second classification, and a third classification.

5. The integrated circuit as set forth in claim 4, further comprising an auto saving configuration circuit adapted to receive the plurality of parameters and store the plurality of parameters in the fuse information memory block and, when the classification is one of a group consisting of the first classification and the third classification, readjust the internal timing circuit to cause the classification of the plurality of samples to move toward the second classification.