Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

• US 8,595,669 B1
• Filed: 09/02/2008
• Issued: 11/26/2013
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Keller, Igor, Kariat, Vinod, Tam, King Ho
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US12/203,128
• Time in Patent Office: 1,911 Days
• Field of Search: 716/106, 716/108, 716/113, 716/114, 716/115, 716/132, 716/134, 716/136, 703/2, 703/14
• US Class Current: 716/115
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.

Claims

1. A system for static noise analysis of an integrated circuit design, the system comprising:

a processor to execute instructions to perform operations in analyzing an integrated circuit design; and

a non-transitory processor readable medium to store instructions that when executed by the processor cause the processor to perform operations including;

presenting a plurality of selectable noise analysis components to a user to analyze noise induction into one or more stages of standard cell logic gates alone a delay path, each of the plurality of selectable noise analysis components having a plurality of choices;

receiving a user selected choice for each of the plurality of selectable noise analysis components; and

statically analyzing noise effects on the one or more stages of standard cell logic gates along the delay path within the integrated circuit design in response to the user selected choice for each of the plurality of selectable noise analysis components.

2. The system of claim 1, wherein the processor executes further instructions to perform operations of:

modeling a victim driver in each circuit stage of the integrated circuit design with a multi-CCC current source model in response to the user selected choice for a first selectable noise analysis component; and

modeling one or more aggressor drivers in each circuit stage of the integrated circuit design with one or more multi-CCC current source models in response to the user selected choice for a second selectable noise analysis component.

3. The system of claim 1, wherein the processor executes further instructions to perform operations of:

filtering a plurality of aggressor drivers of each circuit stage as weak aggressor drivers in response to the user selected choice for a third selectable noise analysis component; and

forming a virtual aggressor driver for each circuit stage by combining the weak aggressor drivers together in response to the user selected choice for a fourth selectable noise analysis component.

4. The system of claim 1, further comprising:

a display device coupled to the processor, the display device to present the plurality of selectable noise analysis components to the user with a user interface; and

an input device coupled to the processor, the input device to receive the user selected choice for each of the plurality of selectable noise analysis components.

5. The system of claim 1, wherein:

the plurality of selectable noise analysis components includes an aggressor driver model, a victim driver model, aggressor filtering/constraining, a virtual aggressor driver, aggressor aligning, and a metric or objective measure of noise effects on the integrated circuit design.

6. The system of claim 5, wherein:

the plurality of choices for the aggressor driver model includes

two or more of a voltage source, a linear current source, a non-linear current source, and a transistor-level netlist.

7. The system of claim 5, wherein:

the plurality of choices for the victim driver model includes

two or more of a linear current source, a non-linear current source, and a transistor-level netlist.

8. The system of claim 5, wherein:

the plurality of choices for the aggressor filtering/constraining includes

using a timing window based overlap method to determine subgroups of aggressors that induce crosstalk; and

using a logical relation to determine a subset of aggressor drivers that can switch together.

9. The system of claim 5, wherein:

the plurality of choices for the virtual aggressor driver includes

lumping all aggressor drivers into one virtual aggressor driver on an interconnect network,

lumping a first plurality of aggressor drivers into a first virtual aggressor driver coupled to one end of the interconnect network and lumping a second plurality of aggressor drivers into a second virtual aggressor driver coupled to an opposite end of the interconnect network, and

lumping every third aggressor driver into a virtual aggressor driver coupled the interconnect network.

10. The system of claim 5, wherein:

the plurality of choices for the aggressor aligning includes

a partial alignment method, and

a binary alignment method.

11. The system of claim 5, wherein:

the plurality of choices for the metric or objective measure of noise effects on the integrated circuit design includes

glitch peak, glitch energy, and timing delay.

12. A system for static noise analysis of an integrated circuit design, the system comprising:

a processor to execute instructions to perform operations in analyzing an integrated circuit design; and

a non-transitory processor readable medium to store instructions that when executed by the processor cause the processor to perform operations including;

presenting a plurality of selectable noise analysis components to a user, each of the plurality of selectable noise analysis components having a plurality of choices,

receiving a user selected choice for each of the plurality of selectable noise analysis components; and

analyzing noise effects on the integrated circuit design in response to the user selected choice for each of the plurality of selectable noise analysis components including,

aligning input transitions into a plurality of aggressor drivers for each circuit stage in response to the user selected choice for a selectable noise analysis component; and

determining a response of each circuit stage in response to the aligned input transitions of the plurality of aggressor drivers.

13. The system of claim 12, wherein:

the input transitions into the plurality of aggressor drivers for each circuit stage are aligned in response to timing window overlap of possible switching times of two or more aggressor drivers indicating that they induce crosstalk noise.

14. The system of claim 12, wherein:

the input transitions into the plurality of aggressor drivers for each circuit stage are aligned in response to a logical relationship between two or more aggressor drivers indicating that they will switch together.

15. The system of claim 12, wherein the processor executes further instructions to perform operations of:

interpreting the response of each circuit stage with an objective measure in response to the user selected choice for a sixth selectable noise analysis component.

16. The system of claim 15, wherein:

a metric of the objective measure is one of glitch peak, glitch energy, and timing delay.

17. A machine readable product for static noise analysis of an integrated circuit design, the machine readable product comprising:

a non-transitory machine readable medium having stored therein;

machine readable program code to automatically present a plurality of selectable noise analysis components to a user to analyze noise induction into one or more stages of standard cell logic gates along a delay path, each of the plurality of selectable noise analysis components having a plurality of choices;

machine readable program code to automatically receive a user selected choice for each of the plurality of selectable noise analysis; and

machine readable program code to automatically and statically analyze noise effects on the one or more stages of standard cell logic gates along the delay path within the integrated circuit design in response to the user selected choice for each of the plurality of selectable noise analysis components.

18. The machine readable product of claim 17, wherein the non-transitory machine readable medium further has stored therein:

machine readable program code to model a victim driver in each circuit stage of the integrated circuit design with a multi-CCC current source model in response to the user selected choice for a first selectable noise analysis component; and

machine readable program code to model one or more aggressor drivers in each circuit stage of the integrated circuit design with one or more multi-CCC current source models in response to the user selected choice for a second selectable noise analysis component.

19. The machine readable product of claim 18, wherein the non-transitory machine readable medium further has stored therein:

machine readable program code to filter a plurality of aggressor drivers of each circuit stage as weak aggressor drivers in response to the user selected choice for a third selectable noise analysis component;

machine readable program code to form a virtual aggressor driver for each circuit stage by combining the weak aggressor drivers together in response to the user selected choice for a fourth selectable noise analysis component;

machine readable program code to align input transitions into a plurality of aggressor drivers for each circuit stage in response to the user selected choice for a fifth selectable noise analysis component;

machine readable program code to determine a response of each circuit stage in response to the aligned input transitions of the plurality of aggressor drivers; and

machine readable program code to interpret the response of each circuit stage with an objective measure in response to the user selected choice for a sixth selectable noise analysis component.

20. The machine readable product of claim 17, wherein:

the plurality of selectable noise analysis components includes an aggressor driver model, a victim driver model, aggressor filtering/constraining, a virtual aggressor driver, aggressor aligning, and a metric or objective measure of noise effects on the integrated circuit design.

21. The machine readable product of claim 20, wherein:

the plurality of choices for the aggressor driver model includes

two or more of a voltage source, a linear current source, a non-linear current source, and a transistor-level netlist.

22. The machine readable product of claim 20, wherein:

the plurality of choices for the victim driver model includes

two or more of a linear current source, a non-linear current source, and a transistor-level netlist.

23. The machine readable product of claim 20, wherein:

the plurality of choices for the aggressor filtering/constraining includes

using a timing window based overlap method to determine subgroups of aggressors that induce crosstalk, and using a logical relation to determine a subset of aggressor drivers that can switch together.

24. The machine readable product of claim 20, wherein:

the plurality of choices for the virtual aggressor driver includes

lumping all aggressor drivers into one virtual aggressor driver on an interconnect network, lumping a first plurality of aggressor drivers into a first virtual aggressor driver coupled to one end of the interconnect network and lumping a second plurality of aggressor drivers into a second virtual aggressor driver coupled to an opposite end of the interconnect network, and lumping every third aggressor driver into a virtual aggressor driver coupled the interconnect network.

25. The machine readable product of claim 20, wherein:

the plurality of choices for the aggressor aligning includes

a partial alignment method, and a binary alignment method.

26. The machine readable product of claim 20, wherein:

the plurality of choices for the metric or objective measure of noise effects on the integrated circuit design includes

glitch peak, glitch energy, and timing delay.