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Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

  • US 8,595,669 B1
  • Filed: 09/02/2008
  • Issued: 11/26/2013
  • Est. Priority Date: 08/31/2007
  • Status: Active Grant
First Claim
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1. A system for static noise analysis of an integrated circuit design, the system comprising:

  • a processor to execute instructions to perform operations in analyzing an integrated circuit design; and

    a non-transitory processor readable medium to store instructions that when executed by the processor cause the processor to perform operations including;

    presenting a plurality of selectable noise analysis components to a user to analyze noise induction into one or more stages of standard cell logic gates alone a delay path, each of the plurality of selectable noise analysis components having a plurality of choices;

    receiving a user selected choice for each of the plurality of selectable noise analysis components; and

    statically analyzing noise effects on the one or more stages of standard cell logic gates along the delay path within the integrated circuit design in response to the user selected choice for each of the plurality of selectable noise analysis components.

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