Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
First Claim
1. A system for static noise analysis of an integrated circuit design, the system comprising:
- a processor to execute instructions to perform operations in analyzing an integrated circuit design; and
a non-transitory processor readable medium to store instructions that when executed by the processor cause the processor to perform operations including;
presenting a plurality of selectable noise analysis components to a user to analyze noise induction into one or more stages of standard cell logic gates alone a delay path, each of the plurality of selectable noise analysis components having a plurality of choices;
receiving a user selected choice for each of the plurality of selectable noise analysis components; and
statically analyzing noise effects on the one or more stages of standard cell logic gates along the delay path within the integrated circuit design in response to the user selected choice for each of the plurality of selectable noise analysis components.
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Accused Products
Abstract
Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.
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Citations
26 Claims
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1. A system for static noise analysis of an integrated circuit design, the system comprising:
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a processor to execute instructions to perform operations in analyzing an integrated circuit design; and a non-transitory processor readable medium to store instructions that when executed by the processor cause the processor to perform operations including; presenting a plurality of selectable noise analysis components to a user to analyze noise induction into one or more stages of standard cell logic gates alone a delay path, each of the plurality of selectable noise analysis components having a plurality of choices; receiving a user selected choice for each of the plurality of selectable noise analysis components; and statically analyzing noise effects on the one or more stages of standard cell logic gates along the delay path within the integrated circuit design in response to the user selected choice for each of the plurality of selectable noise analysis components. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A system for static noise analysis of an integrated circuit design, the system comprising:
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a processor to execute instructions to perform operations in analyzing an integrated circuit design; and a non-transitory processor readable medium to store instructions that when executed by the processor cause the processor to perform operations including; presenting a plurality of selectable noise analysis components to a user, each of the plurality of selectable noise analysis components having a plurality of choices, receiving a user selected choice for each of the plurality of selectable noise analysis components; and analyzing noise effects on the integrated circuit design in response to the user selected choice for each of the plurality of selectable noise analysis components including, aligning input transitions into a plurality of aggressor drivers for each circuit stage in response to the user selected choice for a selectable noise analysis component; and determining a response of each circuit stage in response to the aligned input transitions of the plurality of aggressor drivers. - View Dependent Claims (13, 14, 15, 16)
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17. A machine readable product for static noise analysis of an integrated circuit design, the machine readable product comprising:
a non-transitory machine readable medium having stored therein; machine readable program code to automatically present a plurality of selectable noise analysis components to a user to analyze noise induction into one or more stages of standard cell logic gates along a delay path, each of the plurality of selectable noise analysis components having a plurality of choices; machine readable program code to automatically receive a user selected choice for each of the plurality of selectable noise analysis; and machine readable program code to automatically and statically analyze noise effects on the one or more stages of standard cell logic gates along the delay path within the integrated circuit design in response to the user selected choice for each of the plurality of selectable noise analysis components. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26)
Specification