Interface system having an interface with signal and ground traces connected to interface pins

• US 8,597,034 B2
• Filed: 03/19/2012
• Issued: 12/03/2013
• Est. Priority Date: 04/06/2011
• Status: Active Grant

• Current Assignee: Smiths Interconnect Americas, Inc.
• Original Assignee: Hypertronics Corporation (Smiths Group International Holdings Ltd.)
• Inventors: Ayzenberg, Mark, Morana, Frank
• Primary Examiner(s): Prasad, Chandrika
• Application Number:
  US13/424,181
• Publication Number:
  US 20120258634A1
• Time in Patent Office: 624 Days
• Field of Search: 439/65, 439/63, 439/79, 439/541.5, 439/843
• US Class Current: 439/65
• CPC Class Codes: H01R 12/737 Printed circuits being substantially perpendicular to each other for printed connections H05K3/366
• CPC Class Codes: H01R 13/187 with spring member in the socket
• CPC Class Codes: H01R 13/33 Contact members made of resilient wire
• CPC Class Codes: H01R 13/6587 for mounting on PCBs
• CPC Class Codes: Y10T 29/49126 Assembling bases

Abstract

An interface system may be used for connecting a mother board with a peripheral device board. The interface system may include a mother interface and a daughter interface. The mother interface may establish a connection portal for the mother board, and the daughter interface may establish a connection portal for the peripheral device board. The interface system may be equipped with a socket with multi-contact surface for providing high speed, high performance, and low noise data transmission. The interface system may be ruggedized with various stabilizing mechanisms, such that it may deliver consistent and reliable performance under harsh military and/or aerospace conditions.

Claims

1. An interface system for connecting a first electrical device board with a second electrical device board, comprising:

a first interface configured to be connected to the first electrical device board and including a signal plane having a plurality of signal traces and an interface pin connected to one of the plurality of signal traces, wherein the plurality of signal traces includes a ground signal trace; and

a second interface configured to be connected to the second electrical device board and having an interface socket, the interface socket configured to receive the interface pin and establish a plurality of contact lines distributed across a surface of the interface pin.

2. The interface system of claim 1 wherein each of the plurality of contact lines has an angular gradation.

3. The interface system of claim 1 wherein the interface socket is configured to apply a set of normal forces radially across the surface of the interface pin.

4. The interface system of claim 1 wherein the interface socket further comprises a socket wire sleeve having a plurality of contact wires for establishing the plurality of contact lines distributed across the surface of the interface pin.

5. The interface system of claim 4 wherein the plurality of contact wires of the socket wire sleeve are twisted to form a helicoidal mesh surface.

6. The interface system of claim 1 wherein the first interface further comprises:

a connecting surface configured to face the first electrical device board;

a connecting pin protruding from the connecting surface and configured to be inserted into the first electrical device board; and

an interface surface supporting the interface pin and configured to be positioned perpendicular to the connecting surface.

7. The interface system of claim 6 wherein the connecting pin is electrically coupled with the interface pin.

8. The interface system of claim 1 wherein the second interface further comprises:

a connecting surface configured to face the second electrical device board;

a connecting pin protruding from the connecting surface and configured to be inserted into the second electrical device board; and

an interface surface supporting the interface socket and opposing the connecting surface.

9. The interface system of claim 8 wherein the connecting pin is electrically coupled with the interface socket.

10. An interface system for connecting a mother board with a peripheral device board, comprising:

a daughter interface configured to be connected to the peripheral device board and having a plurality of interface pins, the daughter interface including;

a signal frame including a plurality of signal traces, the plurality of interface pins connected respectively to the plurality of signal traces, the plurality of signal traces including a ground signal trace;

a daughter-interface connecting surface configured to face the peripheral device board,

a daughter-interface interface surface positioned perpendicular to the daughter-interface connecting surface and supporting the plurality of interface pins, and

a plurality of daughter-interface connecting pins protruding from the daughter-interface connecting surface, connected respectively to the plurality of signal traces and configured to be inserted into the peripheral device board; and

a mother interface configured to be connected to the mother board and having a plurality of interface sockets, each interface socket configured to receive one of the plurality of interface pins and establish a plurality of contact lines distributed across a surface of the corresponding interface pin, the mother interface including;

a mother-interface connecting surface configured to face the mother board,

a mother-interface interface surface opposing the mother-interface connecting surface and supporting the plurality of interface sockets, and

a plurality of mother-interface connecting pins protruding from the mother-interface connecting surface and configured to be inserted into the mother board.

11. The interface system of claim 10 wherein each of the plurality of interface sockets is configured to apply a set of normal forces against the surface of the corresponding interface pin.

12. The interface system of claim 10 wherein each of the plurality of interface sockets is configured to grip the corresponding interface pin with an angular gradation for smooth insertion or extraction of the corresponding interface pin.

13. The interface system of claim 10 wherein the mother interface further comprises a bracket positioned perpendicular to the mother-interface interface surface for protecting a space adjacent to the plurality of interface sockets.

14. The interface system of claim 10 wherein the daughter interface comprises a wafer housing defining a cavity therein, a plurality of signal traces positioned within the cavity of the wafer housing and electrically connecting each of the plurality of daughter-interface connecting pins to one of the interface pins.

15. The interface system of claim 14 wherein the wafer housing further comprises a slot for allowing air flow through the cavity of the wafer housing.

16. The interface system of claim 10 wherein each of the plurality of mother-interface connecting pins is mechanically coupled to one of the plurality of interface sockets to form a plurality of hybrid units, each hybrid unit having a pin end and a socket end.

17. The interface system of claim 16 wherein the mother-interface connecting surface defines a plurality of ports and each of the plurality of hybrid units is positioned in one of the plurality of ports.

18. The interface system of claim 17 further comprising a plurality of polytetrafluoroethylene (PTFE) spacers, each of the plurality of PTFE spacers surrounding one of the hybrid units and positioned in one of the plurality of ports for controlling an impedance through the surrounded hybrid unit.

19. A method for interfacing a first device board with a second device board, comprising:

establishing a first interface including a signal plane having a plurality of signal traces and an interface pin connected to one of the plurality of signal traces and configured to be connected to the first device board, wherein the plurality of signal traces includes a ground signal trace;

establishing a second interface having an interface socket and configured to be connected to the second board; and

receiving the interface pin within the interface socket to establish a plurality of contact lines having an angular gradation across a surface of the interface pin.

20. The method of claim 19 wherein the interface socket is configured to apply a set of normal forces against the surface of the interface pin when the interface pin is received by the interface socket.