Multilevel-cell memory structures employing multi-memory layers with tungsten oxides and manufacturing method
First Claim
1. A method for manufacturing a memory device, comprising:
- forming a first electrode comprising a metal material, the first electrode extending to a top surface of a dielectric layer;
etching the first electrode to remove a portion of the first electrode, thereby forming a recess extending below the top surface of the dielectric layer;
forming a dielectric sidewall spacer within the recess and on the first electrode, the dielectric sidewall spacer having an inner surface defining an opening within the recess, the opening overlying an exposed portion of the first electrode;
oxidizing the exposed portion of the first electrode to form a metal oxide memory element comprising an oxide of said metal material embedded within the first electrode; and
forming a second electrode in contact with the metal oxide memory element.
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Abstract
The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
22 Citations
12 Claims
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1. A method for manufacturing a memory device, comprising:
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forming a first electrode comprising a metal material, the first electrode extending to a top surface of a dielectric layer; etching the first electrode to remove a portion of the first electrode, thereby forming a recess extending below the top surface of the dielectric layer; forming a dielectric sidewall spacer within the recess and on the first electrode, the dielectric sidewall spacer having an inner surface defining an opening within the recess, the opening overlying an exposed portion of the first electrode; oxidizing the exposed portion of the first electrode to form a metal oxide memory element comprising an oxide of said metal material embedded within the first electrode; and forming a second electrode in contact with the metal oxide memory element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for manufacturing a memory device, comprising:
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forming a first electrode comprising a metal extending through a dielectric layer to an underlying bit line; forming a metal oxide memory element electrically coupled to the first electrode by oxidizing a portion of the metal of the first electrode; and forming a second electrode electrically coupled to the metal oxide memory element and in direct and physical contact with the metal oxide memory element, wherein the metal oxide memory element has a width transverse to an inter-electrode current path between the first and second electrodes through the metal oxide memory element which is less than a width of a top electrode surface of the first electrode. - View Dependent Claims (10)
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11. A method for manufacturing a memory device, comprising:
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forming a diode; forming a metal element overlying and electrically coupled to the diode; forming a memory element comprising a metal oxide active layer by oxidizing a portion of the metal element; and forming an electrode overlying and electrically coupled to the metal oxide memory element and in direct and physical contact with the metal oxide memory element, wherein the metal oxide memory element has a width transverse to an inter-electrode current path between the diode and the electrode and through the metal oxide memory element which is less than a width of the diode. - View Dependent Claims (12)
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Specification