Power MOS device fabrication

• US 8,597,998 B2
• Filed: 09/05/2012
• Issued: 12/03/2013
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Lui, Sik K., Li, Tiesheng
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US13/604,286
• Publication Number:
  US 20120329225A1
• Time in Patent Office: 454 Days
• Field of Search: 438/259, 438/271, 438/270
• US Class Current: 438/259
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a mask on a substrate having a top substrate surface;

forming a gate trench in the substrate, through the mask;

depositing gate material in the gate trench;

removing the mask to leave a gate structure;

implanting a body region;

implanting a source region;

forming a source body contact trench having a trench wall and a trench bottom;

forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region;

disposing conductive material in the source body contact trench, on top of the plug;

disposing a conductive contact layer along at least a portion of the trench wall, wherein the conductive contact layer is in contact with at least a portion of the source region; and

forming a drain;

wherein;

the conductive contact layer and the drain form a Schottky diode.

2. The method of claim 1, further comprising disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom.

3. The method of claim 2, wherein the anti-punch through implant includes a region heavily doped with P type material.

4. The method of claim 2, wherein:

the anti-punch through region has a cross sectional depth measured in the direction perpendicular to the trench wall of the source body contact trench, and a cross sectional length that is measured in the direction along the source body contact trench wall; and

the cross sectional depth is substantially less than the cross sectional length.

5. The method of claim 1, wherein the body region has a body top surface, and the gate structure has a gate top surface that extends substantially above the body top surface.

6. The method of claim 1, wherein the source region has a source top surface, and the gate structure has a gate top surface that extends substantially above the source top surface.

7. The method of claim 1, further comprising forming an electrode within the source body contact trench, such that the electrode is at least in part in physical contact with the source and at least in part in physical contact with an anti-punch through implant.

8. The method of claim 7, wherein forming the electrode includes using a metal that is suitable for providing Ohmic contact to the source region and the body region.

9. The method of claim 7, wherein forming the electrode includes using a metal that is suitable for forming a Schottky diode with the drain.

10. The method of claim 7, wherein forming the electrode includes using a metal that is suitable for both providing Ohmic contact to the source region and the body regions and for forming a Schottky diode to the drain.

11. The method of claim 7, wherein the electrode and the drain form a Schottky diode.

12. The method of claim 7, wherein the electrode and the drain form a Schottky diode situated below a body diode of the device.

13. The method of claim 7, wherein the electrode and the drain form a Schottky diode, and wherein a metal layer is disposed over the electrode to form a source body contact.

14. The method of claim 7, wherein the source body contact trench extends through the body region to the drain.

15. The method of claim 1, wherein the source body contact trench is formed to have a smooth shape.

16. A method of fabricating a semiconductor device, comprising:

forming a mask on a substrate having a top substrate surface;

forming a gate trench in the substrate, through the mask;

depositing gate material in the gate trench;

removing the mask to leave a gate structure;

implanting a body region;

implanting a source region;

forming a source body contact trench having a trench wall and a trench bottom;

forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region;

disposing conductive material in the source body contact trench, on top of the plug; and

disposing an anti-punch through implant along at least a section of the trench wall but not along the trench bottom;

wherein

the anti-punch through implant does not extend substantially below top surface of the plug.

17. A method of fabricating a semiconductor device, comprising:

forming a mask on a substrate having a top substrate surface;

forming a gate trench in the substrate, through the mask;

depositing gate material in the gate trench;

removing the mask to leave a gate structure;

implanting a body region;

implanting a source region;

forming a source body contact trench having a trench wall and a trench bottom;

forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region;

disposing conductive material in the source body contact trench, on top of the plug; and

disposing a conductive contact layer along at least a portion of the trench wall, wherein

the plug comprises a dielectric material overlaying a portion of the conductive contact layer.