Strain preserving ion implantation methods

• US 8,598,006 B2
• Filed: 03/16/2010
• Issued: 12/03/2013
• Est. Priority Date: 03/16/2010
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation, Kioxia Corporation
• Original Assignee: International Business Machines Corporation, Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Inventors: de Souza, Joel P., Hamaguchi, Masafumi, Ozcan, Ahmet S., Sadana, Devendra K., Saenger, Katherine L., Wall, Donald R.
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US12/724,608
• Publication Number:
  US 20110230030A1
• Time in Patent Office: 1,358 Days
• Field of Search: 438/303, 438/525, 438/300, 438/151, 438/698, 438/276, 257/350, 257/192, 257/368, 257/288
• US Class Current: 438/303
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26593 at a temperature lower than room temperature
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.

Claims

1. A method of performing processing steps for forming a semiconductor structure, said processing steps comprising:

providing a semiconductor substrate including a first single crystalline semiconductor material;

forming a strained semiconductor material portion directly on said semiconductor substrate, wherein said strained semiconductor material portion comprises a second single crystalline semiconductor material and is epitaxially aligned to, and is lattice-mismatched relative to, said first single crystalline semiconductor material of said semiconductor substrate, wherein a lattice mismatch between said first semiconductor material and said second semiconductor material is a source of a strain exerted on said strained semiconductor material portion by said first semiconductor material in said semiconductor substrate;

reducing a magnitude of said strain exerted on said strained semiconductor material portion by rendering said strained semiconductor material portion substantially amorphous through ion implantation of dopant ions into said strained semiconductor material portion without implanting said dopant ions into said first single crystalline semiconductor material at a cooled temperature within a range from −

267 degrees Celsius to 10 degrees Celsius; and

generating a residual strain in said strained semiconductor material portion by annealing said implanted strained semiconductor material portion at a temperature that removes structural damages induced by implantation of said dopant ions.

3. The method of claim 1, wherein said processing steps further comprise forming a gate dielectric and a gate electrode on said semiconductor substrate, wherein said strained semiconductor material portion is formed self-aligned to said gate electrode.

4. The method of claim 1, wherein said dopant ions are p-type dopant ions or n-type dopant ions.

5. The method of claim 1, wherein said dopant ions include at least one of B, BF₂, Ga, In, P, As, and Sb.

2. A method of performing processing steps for forming a semiconductor structure, said processing steps comprising:

providing a semiconductor substrate including a first single crystalline semiconductor material;

forming a strained semiconductor material portion directly on said semiconductor substrate, wherein said strained semiconductor material portion comprises a second single crystalline semiconductor material and is epitaxially aligned to, and is lattice-mismatched relative to, said first single crystalline semiconductor material of said semiconductor substrate, wherein a lattice mismatch between said first semiconductor material and said second semiconductor material is a source of a strain exerted on said strained semiconductor material portion by said first semiconductor material in said semiconductor substrate, wherein said first single crystalline semiconductor material of said semiconductor substrate is silicon, and said strained semiconductor material portion comprises a silicon germanium carbon alloy;

reducing a magnitude of said strain exerted on said strained semiconductor material portion by rendering said strained semiconductor material portion substantially amorphous through ion implantation of dopant ions into said strained semiconductor material portion without implanting said dopant ions into said first single crystalline semiconductor material at a cooled temperature within a range from −

267 degrees Celsius to 10 degrees Celsius; and

generating a residual strain in said strained semiconductor material portion by annealing said implanted strained semiconductor material portion at a temperature that removes structural damages induced by implantation of said dopant ions.

6. A method of performing processing steps for forming a semiconductor structure, said processing steps comprising:

providing a semiconductor substrate including a first single crystalline semiconductor material;

forming a strained semiconductor material portion directly on said semiconductor substrate, wherein said strained semiconductor material portion comprises a second single crystalline semiconductor material and is epitaxially aligned to, and is lattice-mismatched relative to, said first single crystalline semiconductor material of said semiconductor substrate, wherein a lattice mismatch between said first semiconductor material and said second semiconductor material is a source of a strain exerted on said strained semiconductor material portion by said first semiconductor material in said semiconductor substrate;

implanting first dopant ions into said strained semiconductor material portion at a non-amorphizing dose at a first temperature within a range from 30 degrees Celsius to 700 degrees;

reducing a magnitude of said strain exerted on said strained semiconductor material portion by rendering said strained semiconductor material portion substantially amorphous through ion implantation of second dopant ions into said strained semiconductor material portion without implanting said second dopant ions into said first single crystalline semiconductor material at a second temperature within a range from −

267 degrees Celsius to 10 degrees Celsius; and

generating a residual strain in said strained semiconductor material portion by annealing said strained semiconductor material portion after implanting said first and second dopant ions at a temperature that removes structural damages induced by implantation of said second dopant ions.

7. The method of claim 6, wherein said semiconductor material of said semiconductor substrate is silicon, and said strained semiconductor material portion comprises one of a silicon germanium alloy, a silicon carbon alloy, and a silicon germanium carbon alloy.

8. The method of claim 6, wherein said processing steps further comprise forming a gate dielectric and a gate electrode on said semiconductor substrate, wherein said strained semiconductor material portion is formed self-aligned to said gate electrode.

9. The method of claim 6, wherein said dopant ions are p-type dopant ions or n-type dopant ions.

10. The method of claim 9, wherein each of said first dopant ions and said second dopant ions include at least one of B, BF₂, Ga, In, P, As, and Sb.

11. A method of performing processing steps for forming a semiconductor structure, said processing steps comprising:

forming a gate dielectric and a gate electrode on a top surface of a single crystalline semiconductor layer comprising a first single crystalline semiconductor material and having a doping of a first conductivity type and located in a semiconductor substrate;

forming at least one strained semiconductor material portion comprising a second single crystalline semiconductor material and directly on said single crystalline semiconductor layer, wherein said at least one strained semiconductor material portion is epitaxially aligned to, and is lattice-mismatched relative to, said first single crystalline semiconductor material of said single crystalline semiconductor layer, wherein a lattice mismatch between said first semiconductor material and said second semiconductor material is a source of a strain exerted on said at least one strained semiconductor material portion by said first semiconductor material in said semiconductor substrate;

performing a halo ion implantation at a first temperature within a range from 30 degrees Celsius to 700 degrees Celsius, wherein dopant ions of said first conductivity type are implanted into said at least one strained semiconductor material portion at a non-amorphizing dose;

reducing a magnitude of said strain exerted on said at least one strained semiconductor material portion by rendering said at least one strained semiconductor material portion substantially amorphous by a source/drain ion implantation of second dopant ions at a second temperature within a range from −

267 degrees Celsius to 10 degrees Celsius into said at least one strained semiconductor material portion without implanting said second dopant ions into said first single crystalline semiconductor material; and

generating a residual strain in said strained semiconductor material portion by annealing said at least one strained semiconductor material portion after performing said halo ion implantation and said source/drain ion implantation at a temperature that removes structural damages induced by implantation of said second dopant ions.

12. The method of claim 11, wherein said single crystalline semiconductor layer is a silicon layer, and said at least one strained semiconductor material portion comprises one of a silicon germanium alloy, a silicon carbon alloy, and a silicon germanium carbon alloy.

13. The method of claim 11, wherein said first temperature is between 100 degrees Celsius and 600 degrees Celsius, and wherein said second temperature is between −

200 degrees Celsius and 0 degrees Celsius.

14. The method of claim 13, wherein said first temperature is between 200 degrees Celsius and 500 degrees Celsius, and wherein said second temperature is between −

200 degrees Celsius and −

50 degrees Celsius.

15. The method of claim 11, wherein said processing steps further comprise performing a source/drain extension ion implantation at a third temperature within a range from −

267 degrees Celsius to 10 degrees Celsius, wherein dopants of said second conductivity type are implanted into said at least one strained semiconductor material portion at an amorphizing dose employing said gate electrode as a self-aligning implantation mask.

16. The method of claim 11, wherein said strained semiconductor material portion is formed self-aligned to said gate electrode, and wherein each of said dopants of said first conductivity type and said dopants of said second conductivity type include at least one of B, BF₂, Ga, In, P, As, and Sb.